參數(shù)資料
型號： 935264570557
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), SERIAL COMM CONTROLLER, PQFP80
封裝： 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80
文件頁數(shù)： 36/36頁
文件大?。?/td> 145K
代理商： 935264570557
2000 Nov 17
9
Philips Semiconductors
Preliminary specication
1394 SBP-2 link layer controller
SAA7356HL
7
FUNCTIONAL DESCRIPTION
7.1
Overview
The SAA7356HL is an IEEE1394-1995 and P1394a
compliant link layer controller. It provides a direct interface
between a 1394 bus and a DMA interface found on many
buffer managers (see Fig.3). Through this interface, the
SBP-2 automation engine performs all transaction layer
specific operations; these include the management agent,
fetch agent, and page table handling features.
The SBP-2 link also provides an interface to an external
microcontroller. The microcontrollers supported include
8/16-bit addressing from the Intel 8031 derivatives, the
Hitachi H8 and the NEC V851. Through this interface, the
microcontroller retrieves the 12-byte Command Descriptor
Blocks (CDBs) and provides the command status
indication; unsolicited status information is also supported.
handbook, full pagewidth
GSA039
SAA7356HL
IEEE1394/P1394a
SBP-2 LINK LAYER CONTROLLER
MICRO_ADDR [7:0]
MICRO_DATA [7:0]
MICRO_SEL [1:0]
PHY_DATA [0:7]
MICRO_ALE
PHY_CTRL [0:1]
MICRO_READ
PHY_LREQ
MICRO_WRITE
PHY_ISO
MICRO_CS
PHY_SCLK
1349-MODE(1)
MICRO_INT
VDD
VSS
DMA_REQ
DMA_DATA [15:0]
DMA_ACK
DMA
interface
1394 PHY
interface
microcontroller
interface
RESET
DMA_READ
DMA_WRITE
Fig.3 Functional diagram.
(1) Acts as the MICRO_WAIT line when the V851 microcontroller interface mode is selected.
7.2
SBP-2 automation engine
The complete SBP-2 transaction layer is supported by the
SAA7356HL. This includes the log-in, log-out and
reconnect functions in the management agent plus the
fetch engine for retrieving linked lists of Operation Request
Blocks (ORBs) from the logged-in node. The data
transfers plus the required flow control and target node
page-table management are also supported. The
transaction layer parses the ORBs to extract the CDBs and
presents them to the microcontroller. The microcontroller
returns status indication to the transaction layer: the
SBP-2 engine then returns this information plus the
transaction status information to the logged-in node.
The SAA7356HL will present all Configuration-ROM reads
to the microcontroller.
The microcontroller will return the requested information.
The SAA7356HL will then add the required header for the
1394 transaction to service these requests.
7.3
DMA interface
The SAA7356HL supports many formats of DMA interface.
The DMA bus width may be 8 or 16 bits wide. The polarity
of the request, acknowledge, read and write strobes can
be configured for active HIGH or active LOW. The DMA
controller may also be configured as a master or a slave.
In the slave mode, the burst length can also be configured.
All configuration details are loaded into the SAA7356HL
via a shared page in the Static Random Access Memory
(SRAM).
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