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參數(shù)資料
| 型號： | 935264570557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), SERIAL COMM CONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 32/36頁 |
| 文件大小： | 145K |
| 代理商： | 935264570557 |
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2000 Nov 17
5
Philips Semiconductors
Preliminary specication
1394 SBP-2 link layer controller
SAA7356HL
6
PIN CONFIGURATION
SYMBOL
PIN
TYPE(1)
DESCRIPTION
MICRO_ADDR[0]
1
I
microcontroller address input (bit 0); note 2
MICRO_ADDR[1]
2
I
microcontroller address input (bit 1); note 2
MICRO_ADDR[2]
3
I
microcontroller address input (bit 2); note 2
MICRO_ADDR[3]
4
I
microcontroller address input (bit 3); note 2
VDD1(P)
5
S
supply voltage 1 for periphery
VSS1(P)
6
S
ground 1 for periphery
MICRO_ADDR[4]
7
I
microcontroller address input (bit 4); note 2
MICRO_ADDR[5]
8
I
microcontroller address input (bit 5); note 2
MICRO_ADDR[6]
9
I
microcontroller address input (bit 6); note 2
MICRO_ADDR[7]
10
I
microcontroller address input (bit 7); note 2
VDD2(P)
11
S
supply voltage 2 for periphery
VSS2(P)
12
S
ground 2 for periphery
DMA_DATA[15]
13
I /O
DMA data input/output (bit 15); note 3
DMA_DATA[14]
14
I /O
DMA data input/output (bit 14); note 3
DMA_DATA[13]
15
I /O
DMA data input/output (bit 13); note 3
DMA_DATA[12]
16
I /O
DMA data input/output (bit 12); note 3
DMA_DATA[11]
17
I /O
DMA data input/output (bit 11); note 3
DMA_DATA[10]
18
I /O
DMA data input/output (bit 10); note 3
VDD1(C)
19
S
supply voltage 1 for core
VSS1(C)
20
S
ground 1 for core
DMA_DATA[9]
21
I /O
DMA data input/output (bit 9); note 3
DMA_DATA[8]
22
I /O
DMA data input/output (bit 8); note 3
DMA_DATA[7]
23
I /O
DMA data input/output (bit 7); note 3
DMA_DATA[6]
24
I /O
DMA data input/output (bit 6); note 3
DMA_DATA[5]
25
I /O
DMA data input/output (bit 5); note 3
DMA_DATA[4]
26
I /O
DMA data input/output (bit 4); note 3
DMA_DATA[3]
27
I /O
DMA data input/output (bit 3); note 3
DMA_DATA[2]
28
I /O
DMA data input/output (bit 2); note 3
VSS3(P)
29
S
ground 3 for periphery
VDD3(P)
30
S
supply voltage 3 for periphery
DMA_DATA[1]
31
I /O
DMA data input/output (bit 1); note 3
DMA_DATA[0]
32
I /O
DMA data input/output (bit 0); note 3
DMA_REQ
33
O
DMA request signal output in slave mode (acknowledge in master/ATA mode)
(may be congured for active HIGH or active LOW)
DMA_ACK
34
I
DMA acknowledge signal input in slave mode (request in master/ATA mode)
(may be congured for active HIGH or active LOW)
VSS2(C)
35
S
ground 2 for core
VDD2(C)
36
S
supply voltage 2 for core
DMA_READ
37
I /O
DMA read strobe input/output (may be congured for active HIGH or active
LOW)
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