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參數(shù)資料
| 型號： | 935264570557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), SERIAL COMM CONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 145K |
| 代理商： | 935264570557 |
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2000 Nov 17
20
Philips Semiconductors
Preliminary specication
1394 SBP-2 link layer controller
SAA7356HL
12 AC CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DMA INTERFACE WRITE/READ TIMING FOR SLAVE MODE 0; see Fig.8
t0
cycle time
67
ns
t1
DMA_REQ de-assert from DMA_ACK assert
(single word DMA)
25
ns
t2
DMA_REQ de-assert from DMA_WRITE assert
(multi-word DMA)
25
ns
t3
DMA_REQ de-assert from DMA_READ assert
(multi-word DMA)
25
ns
t4
DMA_REQ assert after DMA_ACK de-assert
8
ns
t5
write data set-up
15
ns
t6
write data hold
5
ns
t7
DMA_WRITE active pulse duration
25
ns
t8
read data stable after DMA_READ active
10
ns
t9
read data 3-state after DMA_READ inactive
5
10
ns
t10
DMA_REQ assert after DMA_READ and
DMA_WRITE negated
68
ns
DMA INTERFACE WRITE/READ TIMING FOR SLAVE MODE 1; see Fig.9
t0
cycle time
67
ns
t1
DMA_REQ de-assert from DMA_ACK assert
(single word DMA)
25
ns
t2
DMA_REQ de-assert from DMA_WRITE assert
(multi-word DMA)
25
ns
t3
DMA_REQ assert after DMA_ACK de-assert
5
ns
t4
read data stable after DMA_ACK assert
10
ns
t5
read data 3-state after DMA_ACK inactive
5
10
ns
t6
write data set-up
15
ns
t7
write data hold
5
ns
t8
DMA_WRITE active pulse width
25
ns
DMA INTERFACE WRITE/READ TIMING FOR SLAVE MODE 2; see Fig.10
t0
cycle time
67
ns
t1
DMA_REQ de-assert from DMA_ACK assert
(single word DMA)
25
ns
t2
DMA_REQ assert after DMA_ACK de-assert
5
ns
t3
write data set-up
15
ns
t4
write data hold
5
ns
t5
DMA_ACK active pulse duration during data write
25
ns
t6
read data stable after DMA_ACK assert
10
ns
t7
read data 3-state after DMA_ACK de-assert
5
10
ns
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