參數(shù)資料
型號(hào)： 935263912551
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1 MM HEIGHT, PLASTIC, SOT-386-1, TQFP-100
文件頁(yè)數(shù)： 28/56頁(yè)
文件大?。?/td> 277K
代理商： 935263912551
Philips Semiconductors
Preliminary specification
PDI1394L21
1394 full duplex AV link layer controller
2000 Jun 06
34
13.2.2
Common Isochronous Transmit Packet Header Quadlet 1 (ITXHQ1) – Base Address: 0x024
The AV Transmit Packing Control register holds the specification for the packing scheme used on the AV data stream. This information is
included in Common Isochronous Packet (CIP) header quadlet 1.
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPH
QPC
FN
DBS
SV01747
31 30
Reset Value 0x00000000
Bit 16..23:
R/W
DBS: Size of the data blocks from which AV payload is constructed. The value 0 represents a length of 256 quadlets.
Bit 14..15:
R/W
FN: (Fraction Number) The encoding for the number of data blocks into which each source packet shall be divided
(00 = 1, 01 = 2, 10 = 4, 11 = 8).
Bit 11..13:
R/W
QPC: Number of dummy quadlets to append to each source packet before it is divided into data blocks of the
specified size. The value QPC must be less than DBS and less than 2FN.
Bit 10:
R/W
SPH: Indicates that a 25-bit CYCTM based time stamp has to be inserted before each application packet.
13.2.3
Common Isochronous Transmit Packet Header Quadlet 2 (ITXHQ2) – Base Address: 0x028
The contents of this register are copied to the second quadlet of the CIP header and transmitted with each isochronous packet.
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMT
FDF
SV00281
31 30
SYT
Reset Value 0x00000000
Bit 29..24:
R/W
FMT: Value to be inserted in the FMT field in the AV header.
Bit 23..0:
R/W
FDF/SYT: Value to be inserted in the FDF field. When the EN_FS bit in the Transmit Control and Status Register
(ITXPKCTL) is set (=1), the lower 16 bits of this register are replaced by an SYT stamp if a rising edge on
AVFSYNCIN has been detected or all ‘1’s if no such edge was detected since the previous packet. The upper 8 bits
of the register are sent as they appear in the FDF register. When the EN_FS bit in the Transmit Control and Status
Register is unset (=0), the full 24 bits can be set to any application specified value.
相關(guān)PDF資料
PDF描述
08-1101-00 DREHSCHALTER 1POL 12STELLUNGEN
08-1260-00 ************GESTRICHEN************
08-1341-00 DREHSCHALTER 3POL 4STELLUNGEN
08-2101-00 DREHSCHALTER 2POL 12STELLUNGEN
08-2261-00 DREHSCHALTER 4POL 6STELLUNGEN
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