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參數(shù)資料
| 型號： | 935263593118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | AHC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20 |
| 封裝： | 4.40 MM, PLASTIC, MO-153AC, SOT-360-1, TSSOP-20 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 92K |
| 代理商： | 935263593118 |
1999 Sep 01
11
Philips Semiconductors
Product specication
Octal D-type ip-op with reset;
positive-edge trigger
74AHC273; 74AHCT273
Type 74AHCT273
Ground = 0 V; tr =tf ≤ 3.0 ns.
Note
1. Typical values at VCC = 5.0 V.
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb (°C)
UNIT
WAVEFORMS
CL
25
40 to +85
40 to +125
MIN.
TYP.
MAX. MIN.
MAX.
VCC = 4.5 to 5.5 V; note 1
tPHL/tPLH
propagation delay
CP to Qn
see Figs 6 and 9
15 pF
4.0
7.5
1.0
8.8
1.0
9.5
ns
tPHL
propagation delay
MR to Qn
see Figs 7 and 9
3.9
10.0
1.0
11.6
1.0
12.5
ns
fmax
maximum clock
pulse frequency
75
120
65
65
ns
tPHL/tPLH
propagation delay
CP to Qn
see Figs 6 and 9
50 pF
5.8
9.2
1.0
10.5
1.0
11.5
ns
tPHL
propagation delay
MR to Qn
see Figs 7 and 9
5.6
11.0
1.0
12.6
1.0
14.0
ns
tW
clock pulse width
HIGH or LOW
see Figs 6 and 9
5.0
6.5
6.5
ns
master reset
pulse width LOW
see Figs 7 and 9
5.0
6.0
6.0
ns
trem
removal time
MR to CP
2.5
2.5
2.5
ns
tsu
setup time
Dn to CP
see Figs 8 and 9
3.0
3.0
3.0
ns
th
hold time
Dn to CP
1.0
1.0
1.0
ns
fmax
maximum clock
pulse frequency
50
75
45
45
ns
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