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參數(shù)資料
| 型號： | 935263593118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | AHC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20 |
| 封裝： | 4.40 MM, PLASTIC, MO-153AC, SOT-360-1, TSSOP-20 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 92K |
| 代理商： | 935263593118 |
1999 Sep 01
2
Philips Semiconductors
Product specication
Octal D-type ip-op with reset;
positive-edge trigger
74AHC273; 74AHCT273
FEATURES
Ideal buffer for MOS microcontroller or memory
Common clock and master reset
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt trigger actions
Inputs accepts voltages higher than VCC
See ‘377’ for clock enable version
See ‘373’ for transparent latch version
See ‘374’ for 3-state version
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Specified from 40 to +85 °C and 40 to +125 °C.
DESCRIPTION
The 74AHC/AHCT273 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74AHC/AHCT273 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs.
The common clock (CP) and master reset (MR) inputs load
and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Qn) of the flip-flop.
All outputs will be forced LOW independently of clock or
data inputs by a LOW on the MR input.
The device is useful for applications where the true output
only is required and the clock and master reset are
common to all storage elements.
QUICK REFERENCE DATA
Ground = 0 V; Tamb =25 °C; tr =tf ≤ 3.0 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
tPHL/tPLH
propagation delay
CL = 15 pF; VCC =5V
CP to Qn
4.2
4.0
ns
MR to Qn
3.7
3.9
ns
fmax
maximum clock frequency
CL = 15 pF; VCC = 5 V
120
MHz
CI
input capacitance
VI =VCC or GND
3.0
pF
CO
output capacitance
4.0
pF
CPD
power dissipation
capacitance
CL = 50 pF; f = 1 MHz;
notes 1 and 2
14.0
18.0
pF
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