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| 型號(hào)： | 935263331557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP240 |
| 封裝： | 32 X 32 MM, 3.40 MM HEIGHT, MSQFP-240 |
| 文件頁(yè)數(shù)： | 496/518頁(yè) |
| 文件大?。?/td> | 7111K |
| 代理商： | 935263331557 |
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Philips Semiconductors
Cache Architecture
File: cache.fm5, modified 7/24/99
PRELIMINARY INFORMATION
5-5
2. The address is less than the sum of the values in
DC_LOCK_ADDR and DC_LOCK_SIZE.
Programmers (or compilers) must combine all data that
needs to be locked into this single linear address range.
Setting DC_LOCK_ENABLE to ‘1’ causes the following
sequence of events:
1. All blocks that are in cache locations that will be used
for locking are copied back to main memory (if they
are dirty) and removed from the cache.
2. All blocks in the lock range are fetched from main
memory into the cache. If any block in the lock range
was already in the cache, it’s rst copied back (if it’s
dirty) and invalidated.
3. The LRU status of any set that contains locked blocks
is set to the initialization value.
4. Cache locking is activated so that the locked blocks
cannot be victims of the replacement algorithm.
This sequence of events is triggered by writing ‘1’ to
DC_LOCK_ENABLE even if the enable is already set to
‘1’. Setting DC_LOCK_ENABLE to ‘0’ causes no action
except to allow the previously locked blocks to be re-
placement victims.
To program a new lock range, the following sequence of
operations is used:
1. Disable cache locking by writing ‘0’ to
DC_LOCK_ENABLE.
2. Dene a new lock range by writing to
DC_LOCK_ADDR and DC_LOCK_SIZE.
3. Enable cache locking by writing ‘1’ to
DC_LOCK_ENABLE.
Dirty locked blocks can be written back to main memory
while locking is enabled by executing copyback opera-
tions in software.
Programmer’s note: Software should not execute din-
valid operations on a locked block. If it does, the block
will be removed from the cache, creating a ‘hole’ in the
lock range (and the data cache) that cannot be reused
until locking is deactivated.
Cache locking is disabled by default when TM1100 is re-
set.
The RESERVED field in DC_LOCK_CTL should be ig-
nored on reads and written as all zeroes.
Locking should not be enabled by PCI accesses to the
MMIO registers.
5.3.8
Memory Hole and PCI Aperture
Disable
Bits
6
and
5
in
DC_LOCK_CTL
comprise
the
APERTURE_CONTROL field. This field can be used to
change the memory map as seen by the DSPCPU. The
hardware RESET value of the field corresponds to the
memory map as described in Section 3.4.1, “Memory
5.3.9
Non-Cacheable Region
The data cache supports one non-cacheable address re-
gion within the DRAM address space aperture. The base
address of this region is determined by the value in the
DRAM_CACHEABLE_LIMIT MMIO register, which is
shown in Figure 5-6. Since uncached memory opera-
tions always incur many stall cycles, the non-cacheable
region should be used sparingly.
A memory operation is non-cacheable if its target ad-
dress satisfies:
[dram_cacheable_limit] <= address < [dram_limit]
Thus, the non-cacheable region is at the high end of the
DRAM
aperture.
The
format
of
the
DRAM_CACHEABLE_LIMIT register forces the size of
the non-cacheable region to be a multiple of 64 KB.
When TM1100 is reset, DRAM_CACHEABLE_LIMIT is
set equal to DRAM_LIMIT, which results in a zero-length
non-cacheable region.
Programmer’s note: When DRAM_CACHEABLE_LIMIT
is changed to enlarge the region that is non-cacheable,
software must assure coherency. This is accomplished
by explicitly copying back dirty data (using dcb opera-
tions) and invalidating (using dinvalid operations) the
cache blocks in the previously unlocked region.
5.3.10
Special Data Cache Operations
A program can exercise some control over the operation
of the data cache by executing special operations. The
special operations can cause the data cache to initiate
the copyback or invalidation of a block in the cache.
Table 5-6. Aperture Control eld
value
Memory Map properties
00 (RESET) normal operation memory map (Section 3.4.1):
loads to 0..0xff always return 0 and cause no
PCI read (memory hole is enabled)
PCI aperture(s) are enabled
01
loads to address 0..0xff cause a PCI read, i.e.
the memory hole is disabled
PCI aperture(s) are enabled
10
PCI apertures are disabled for both loads and
stores
loads return a 0 and cause no PCI read
stores have no effect
11
RESERVED for future extensions
31
0
3
7
11
15
19
23
27
DRAM_CACHEABLE_LIMIT
(r/w)
0x10 0008
DRAM_CACHEABLE_LIMIT_FIELD
0000000000000000
MMIO_BASE
offset:
Figure 5-6 Formats of the DRAM_CACHEABLE_LIMIT register.
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