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| 型號(hào)： | 935263331557 |
| 廠(chǎng)商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP240 |
| 封裝： | 32 X 32 MM, 3.40 MM HEIGHT, MSQFP-240 |
| 文件頁(yè)數(shù)： | 493/518頁(yè) |
| 文件大?。?/td> | 7111K |
| 代理商： | 935263331557 |
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TM1100 Preliminary Data Book
Philips Semiconductors
5-2
PRELIMINARY INFORMATION
File: cache.fm5, modified 7/24/99
wide paths to the caches are matched to the bandwidth
requirements of the DSPCPU.
To improve cache behavior and thus program perfor-
mance, the caches have a locking mechanism. In addi-
tion, the instruction cache is coupled with an instruction
decompression unit. The compressed instruction format
improves the cache hit rate and reduces the bus band-
width required between main memory and cache. In-
structions in main memory and cache use the com-
pressed format.
TM1100’s processing units access the external SDRAM
through the on-chip central “data highway” bus. The
highway consists of separate 32-bit address and data
buses, and use of the bus is mediated by the main-mem-
ory interface unit. The main-memory interface contains
the SDRAM controller and a central arbiter that deter-
mines how much of the available SDRAM memory band-
width is allocated to each unit. Unused bandwidth is al-
ways made available to the VLIW CPU for cache refill
and memory accesses that bypass the caches.
Table 5-2 gives a summary description of each compo-
nent of TM1100’s memory system.
5.2
DRAM APERTURE
TM1100 implements a 32-bit linear address space of
bytes. Within that address space, TM1100 supports sev-
eral different apertures for specific purposes. The DRAM
aperture describes the part of the address space into
which the external SDRAM is mapped. SDRAM must
consist of a single, contiguous region of memory, which
is the most practical configuration for TM1100 systems.
The location and size of the DRAM aperture is defined by
two registers, DRAM_BASE and DRAM_LIMIT. These
registers are both readable and writeable as MMIO reg-
isters and as PCI configuration space registers. The view
of the registers in MMIO space is shown in Figure 5-2.
The view of the registers in PCI configuration space is
described in Chapter 10, “PCI Interface.” In normal oper-
ation, the base address registers are assigned once dur-
ing boot, and not changed when the DSPCPU is running.
Refer to Chapter 10, “PCI Interface,” and Chapter 12,
“System Boot,” for a description of this process.
DRAM_LIMIT must be set equal to DRAM_BASE plus
the actual size of SDRAM present. The amount of the
SDRAM is not required to be a power of two, but it must
be a multiple of 64 KB. Note that the size of the aperture
as set in the PCI configuration space can be larger, be-
cause it must be a power of 2.
A memory operation will access SDRAM if its address
satisfies:
[DRAM_BASE]
≤ address < [DRAM_LIMIT]
Any address outside this range cannot access SDRAM.
When TM1100 is reset, DRAM_BASE_FIELD is set to
0x0 and DRAM_LIMIT is set to 0x0010 0000 (1-MB
DRAM aperture starting at address 0x0). The boot pro-
cess described in Chapter 12, “System Boot,” overrides
these initial settings.
5.3
DATA CACHE
The data cache serves only the DSPCPU and is con-
trolled by two memory units that execute the load and
store operations issued by the DSPCPU. The following
Table 5-2. Summary Of Memory System
Characteristics
Unit
Description
Branch units
Branch units execute branch operations. Up to
three branch operations can be executed in
parallel, but the program must guarantee that
only one branch is taken.
Decompres-
sion unit
Instructions are stored in memory and in the
instruction cache in a space-saving, com-
pressed format. The decompression unit
expands instruction to their full, 28-byte size
before they are issued to the CPU.
Instruction
Cache
The instruction cache holds 32K bytes, is
eight-way set-associative, and has a 64-byte
block size. A miss in a block causes the entire
block to be read from SDRAM. The cache can
sustain an issue rate of one instruction per
cycle on cache hits.
Memory units
Memory units execute load and store opera-
tions. The data cache is dual ported to allow
the memory units to operate concurrently.
Data Cache
The data cache holds 16K bytes, is eight-way
set-associative, has a 64-byte block size, and
implements a copyback, allocate-on-write pol-
icy. A miss in a block causes the entire block
to be read from SDRAM. The cache supports
memory-mapped I/O through non-cacheable
address regions.
Data highway
The on-chip data highway bus serves all on-
chip units. The highway has separate 32-bit
data and address buses. Bandwidth on the
bus is allocated by the highway arbiter accord-
ing to one of several modes.
Main-memory
interface
The main-memory interface contains the data-
highway access arbiter, the SDRAM control-
ler, and MMIO logic.
SDRAM main
memory
External SDRAM connects gluelessly to
TM1100 over the 32-bit main-memory bus.
31
0
3
7
11
15
19
23
27
DRAM_BASE (r/w)
0x10 0000
DRAM_BASE_FIELD
DRAM_LIMIT (r/w)
0x10 0004
DRAM_LIMIT_FIELD
0
00
0
00
0
MMIO_BASE
offset:
0
Figure 5-2. Formats of the DRAM_BASE and DRAM_LIMIT registers.
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