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參數(shù)資料
| 型號： | 935208520112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 5/80頁 |
| 文件大?。?/td> | 446K |
| 代理商： | 935208520112 |
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1997 Dec 15
13
Philips Semiconductors
Product specication
8-bit microcontrollers
P83C524; P80C528; P83C528
8
FUNCTIONAL DESCRIPTION
8.1
General
The P83C524, P80C528 and P83C528 are stand-alone
high-performance microcontrollers designed for use in real
time applications such as instrumentation, industrial
control, medium to high-end consumer applications and
specific automotive control applications.
In addition to the 80C51 standard functions, the devices
provide a number of dedicated hardware functions for
these applications. The P83C524 and P83C528 are
control-oriented CPUs with on-chip program and data
memory. They can be extended with external program
memory up to 64 kbytes. They can also access up to
64 kbytes of external data memory. For systems requiring
extra capability, the P83C524 and P83C528 can be
expanded using standard memories and peripherals.
The P83C524, P80C528 and P83C528 have two software
selectable modes of reduced activity for further power
reduction: Idle and Power-down. The Idle mode freezes
the CPU while allowing the RAM, timers, serial ports and
interrupt system to continue functioning. The Power-down
mode saves the RAM contents but freezes the oscillator
causing all other chip functions to be inoperative except
the WDT if it is enabled. The Power-down mode can be
terminated by an external reset, a WDT overflow, and in
addition, by either of the two external interrupts.
8.2
Instruction Set Execution
The P83C524, P80C528 and P83C528 use the powerful
instruction set of the 80C51. Additional SFRs are
incorporated to control the on-chip peripherals. The
instruction set consists of 49 single-byte, 46 two-byte and
16 three-byte instructions. When using a 16 MHz
oscillator, 64 instructions execute in 750 ns and 45
instructions execute in 1.5 s. Multiply and divide
instructions execute in 3
s (see Chapter 18).
9
MEMORY ORGANIZATION
The central processing unit (CPU) manipulates operands
in three memory spaces; these are the 64 kbyte external
data memory (of which the lower 256 bytes reside in the
internal AUX-RAM), 512 byte internal data memory
(consisting of 256 bytes standard RAM and 256 bytes
AUX-RAM) and the 64 kbyte internal and external program
memory.
9.1
Program Memory
The program memory address space of the P83C528
comprises an internal and an external memory portion.
The P83C528 has 32 kbyte of program memory on-chip.
The program memory can be externally expanded up to 64
kbyte. If the EA pin is held HIGH, the P83C528 executes
out of the internal program memory unless the address
exceeds 7FFFH. Locations 8000H through 0FFFFH are
then fetched from the external program memory. If the EA
pin is held LOW, the P83C528 fetches all instructions from
the external program memory. Fig.6 illustrates the
program memory address space.
By setting a mask programmable security bit the ROM
content is protected i.e. it cannot be read out by any test
mode or by any instruction in the external program
memory space. The MOVC instructions are the only ones
which have access to program code in the internal or
external program memory. The EA input is latched during
RESET and is 'don't care' after RESET. This
implementation prevents reading from internal program
code by switching from external program memory to
internal program memory during MOVC instruction or an
instruction that handles immediate data. Table 2 lists the
access to the internal and external program memory by the
MOVC instructions when the security bit has been set to a
logical one. If the security bit has been set to a logical 0
there are no restrictions for the MOVC instructions.
Fig.6 Program Memory Address Space.
handbook, halfpage
MBC456 - 1
EXTERNAL
64 K
32768
32767
00
PROGRAM MEMORY
32767
EXTERNAL
(EA = 0)
INTERNAL
(EA = 1)
16383 (1)
(1) Only for P83C524.
(EA = 1)
(EA = 0)
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