參數(shù)資料
型號： 935208520112
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 16 MHz, MICROCONTROLLER, PDIP40
封裝： 0.600 INCH, PLASTIC, DIP-40
文件頁數(shù)： 30/80頁
文件大小： 446K
代理商： 935208520112
1997 Dec 15
36
Philips Semiconductors
Product specication
8-bit microcontrollers
P83C524; P80C528; P83C528
Table 20 Description of the S1SCS bits
BIT
SYMBOL
FUNCTION
7
SDO/SDI
Serial Data Output and the ltered Serial Data Input. SDI data is latched on the rising
edge of the ltered serial clock. S1SCS.7 accesses the same memory locations as
S1BIT.7. Access of the data bit via S1SCS will not start an auto-clock pulse.
6
SCO/SCI
Serial Clock Output and the ltered Serial Clock Input. Serial clock output SCO is
'OR-ed' with the auto-clock. If SCO = 1 the auto-clock output is inhibited. The internal
clock stretching logic and external devices can pull the SCL line LOW. If the auto-clock
is not used, the SCL line has to be controlled by setting SCO = 1, waiting for CLH = 1
and setting SCO = 0 after the specied SCL HIGH time. (Because of the input lter,
CLH will be set at least 8 XTAL clock periods after the SCL LOW-to-HIGH transition.)
5
CLH
Serial Clock LOW-to-HIGH transition ag: set with a rising edge of the ltered serial
clock. CLH = 1 indicates that, since the last CLH reset, a new valid data bit has been
latched in SDI. CLH can be reset by writing a 0 to S1SCS.5 or by a read/write of S1BIT.
Clearing CLH also clears RBF and WBF.
4BB
Bus Busy ag: indicating that there has been a START condition that was not yet
followed by a STOP condition.
3
RBF
Read Bit Finished ag: indicating a successful bit read.
RBF = 1 implies the following conditions:
CLH = 1: SCL had a rising edge
SCI = 0: the SCL pulse has finished
SI = 0: no START condition occurred
BB = 1: no STOP condition occurred
The RBF ag can be cleared by clearing the CLH ag.
2
WBF
Write Bit Finished ag: indicating a successful bit write. The same conditions as for
RBF are true and also no 'arbitration loss' condition occurred. Arbitration is lost if a
1 data bit in SDO was over-ruled on SDA by an external device. The WBF ag can be
cleared by clearing the CLH ag.
1
STR
STRetch control ag. STR = 1 enables stretching of all SCL LOW periods. This allows
the processor in I2C slave mode to react on a fast master. The STR ag remains set
until cleared by writing a 0 to S1SCS.1.
The STretch (ST) ag (not readable) pulls the serial clock LOW while ST = 1. The ST
ag is set on the falling edge of the ltered serial clock if STR = 1. It is also set after
reception of a START condition, regardless of the STR contents. ST is cleared with a
read or write of S1BIT.
0
ENS
ENable Serial I/O ag. ENS = 1 enables the START detection and clock stretching
logic. ENS = 0 can be used to switch off the I2C-bus hardware. Note that the SDO and
SCO control ags must be set to 1 before ENS is set to avoid pulling SCL or SDA lines
to 0.
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