參數(shù)資料
型號(hào)： 935143850129
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP28
封裝： 0.600 INCH, PLASTIC, MO-015AH, SOT-117-1, DIP-28
文件頁(yè)數(shù)： 8/34頁(yè)
文件大?。?/td> 313K
代理商： 935143850129
Philips Semiconductors
Product specification
SCN2681
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
16
OPCR – Output Port Configuration Register
OPCR[7] – OP7 Output Select
This bit programs the OP7 output to provide one of the following:
– The complement of OPR[7].
– The Channel B transmitter interrupt output which is the comple-
ment of TxRDYB. When in this mode OP7 acts as an Open- Col-
lector output. Note that this output is not masked by the contents
of the IMR.
OPCR[6] – OP6 Output Select
This bit programs the OP6 output to provide one of the following:
– The complement of OPR[6].
– The Channel A transmitter interrupt output which is the comple-
ment of TxRDYA. When in this mode OP6 acts as an Open-Col-
lector output. Note that this output is not masked by the contents
of the IMR.
OPCR[5] – OP5 Output Select
This bit programs the OP5 output to provide one of the following:
– The complement of OPR[5].
– The Channel B transmitter interrupt output which is the comple-
ment of ISR[5]. When in this mode OP5 acts as an Open-Collector
output. Note that this output is not masked by the contents of the
IMR.
OPCR[4] – OP4 Output Select
This field programs the OP4 output to provide one of the following:
– The complement of OPR[4].
– The Channel B transmitter interrupt output which is the comple-
ment of ISR[1]. When in this mode OP4 acts as an Open-Collec-
tor output. Note that this output is not masked by the contents of
the IMR.
OPCR[3:2] – OP3 Output Select
This bit programs the OP3 output to provide one of the following:
– The complement of OPR[3].
– The counter/timer output, in which case OP3 acts as an Open-
Collector output. In the timer mode, this output is a square wave
at the programmed frequency. In the counter mode, the output
remains High until terminal count is reached, at which time it goes
Low. The output returns to the High state when the counter is
stopped by a stop counter command. Note that this output is not
masked by the contents of the IMR.
– The 1X clock for the Channel B transmitter, which is the clock that
shifts the transmitted data. If data is not being transmitted, a free
running 1X clock is output.
– The 1X clock for the Channel B receiver, which is the clock that
samples the received data. If data is not being received, a free
running 1X clock is output.
OPCR[1:0] – OP2 Output Select
This field programs the OP2 output to provide one of the following:
– The complement of OPR[2].
– The 16X clock for the Channel A transmitter. This is the clock
selected by CSRA[3:0], and will be a 1X clock if
CSRA[3:0] = 1111.
– The 1X clock for the Channel A transmitter, which is the clock that
shifts the transmitted data. If data is not being transmitted, a free
running 1X clock is output.
– The 1X clock for the Channel A receiver, which is the clock that
samples the received data. If data is not being received, a free
running 1X clock is output.
ACR – Auxiliary Control Register
ACR[7] – Baud Rate Generator Set Select
This bit selects one of two sets of baud rates to be generated by the
BRG:
Set 1:
50, 110, 134.5, 200, 300, 600, 1.05k, 1.2k, 2.4k, 4.8k,
7.2k, 9.6k, and 38.4k baud.
Set 2:
75, 110, 134.5, 150, 300, 600, 1.2k, 1.8k, 2.0k, 2.4k, 4.8k,
9.6k, and 19.2k baud.
The selected set of rates is available for use by the Channel A and
B receivers and transmitters as described in CSRA and CSRB.
Baud rate generator characteristics are given in Table 3.
ACR[6:4] – Counter/Timer Mode And Clock Source Select
This field selects the operating mode of the counter/timer and its
clock source as shown in Table 4.
ACR[3:0] – IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable
This field selects which bits of the input port change register (IPCR)
cause the input change bit in the interrupt status register (ISR[7]) to
be set. If a bit is in the ‘on’ state the setting of the corresponding bit
in the IPCR will also result in the setting of ISR[7], which results in
the generation of an interrupt output if IMR[7] = 1. If a bit is in the
‘off’ state, the setting of that bit in the IPCR has no effect on ISR[7].
IPCR – Input Port Change Register
IPCR[7:4] – IP3, IP2, IP1, IP0 Change-of-State
These bits are set when a change-of-state, as defined in the input
port section of this data sheet, occurs at the respective input pins.
They are cleared when the IPCR is read by the CPU. A read of the
IPCR also clears ISR[7], the input change bit in the interrupt status
register. The setting of these bits can be programmed to generate
an interrupt to the CPU.
IPCR[3:0] – IP3, IP2, IP1, IP0 Current State
These bits provide the current state of the respective inputs. The
information is unlatched and reflects the state of the input pins at the
time the IPCR is read.
ISR – Interrupt Status Register
This register provides the status of all potential interrupt sources.
The contents of this register are masked by the Interrupt Mask
Register (IMR). If a bit in the ISR is a ‘1’ and the corresponding bit
in the IMR is also a ‘1’, the INTRN output will be asserted. If the
corresponding bit in the IMR is a zero, the state of the bit in the ISR
has no effect on the INTRN output. Note that the IMR does not
mask the reading of the ISR – the true status will be provided
regardless of the contents of the IMR. The contents of this register
are initialized to 0016 when the DUART is reset.
ISR[7] – Input Port Change Status
This bit is a ‘1’ when a change-of-state has occurred at the IP0, IP1,
IP2, or IP3 inputs and that event has been selected to cause an
interrupt by the programming of ACR[3:0]. The bit is cleared when
the CPU reads the IPCR.
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