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參數(shù)資料
| 型號(hào)： | 935143850129 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, MO-015AH, SOT-117-1, DIP-28 |
| 文件頁數(shù)： | 29/34頁 |
| 文件大小： | 313K |
| 代理商： | 935143850129 |
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Philips Semiconductors
Product specification
SCN2681
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
4
PIN DESCRIPTION
SYMBOL
APPLICABLE
TYPE
NAME AND FUNCTION
SYMBOL
40/44
28
24
TYPE
NAME AND FUNCTION
D0–D7
X
I/O
Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status be-
tween the DUART and the CPU. D0 is the least significant bit.
CEN
X
I
Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the
DUART are enabled on D0-D7 as controlled by the WRN, RDN and A0-A3 inputs. When
High, places the D0-D7 lines in the 3-State condition.
WRN
X
I
Write Strobe: When Low and CEN is also Low, the contents of the data bus is loaded into
the addressed register. The transfer occurs on the rising edge of the signal.
RDN
X
I
Read Strobe: When Low and CEN is also Low, causes the contents of the addressed regis-
ter to be presented on the data bus. The read cycle begins on the falling edge of RDN.
A0–A3
X
I
Address Inputs: Select the DUART internal registers and ports for read/write operations.
RESET
X
I
Reset: A High level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts
OP0–OP7 in the High state, stops the counter/timer, and puts Channels A and B in the inac-
tive state, with the TxDA and TxDB outputs in the mark (High) state. Clears Test modes, sets
MR pointer to MR1.
INTRN
X
O
Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more
of the eight maskable interrupting conditions are true.
X1/CLK
X
I
Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate
frequency (nominally 3.6864 MHz) must be supplied at all times. For crystal connections see
Figure 7, Clock Timing.
X2
X
I
Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin
not connected although it is permissible to ground it.
RxDA
X
I
Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is
High, “space” is Low.
RxDB
X
I
Channel B Receive Serial Data Input: The least significant bit is received first. “Mark” is
High, “space” is Low.
TxDA
X
O
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first.
This output is held in the “mark” condition when the transmitter is disabled, idle or when oper-
ating in local loopback mode. “Mark” is High, “space” is Low.
TxDB
X
O
Channel B Transmitter Serial Data Output: The least significant bit is transmitted first.
This output is held in the “mark” condition when the transmitter is disabled, idle or when oper-
ating in local loopback mode. “Mark” is High, “space” is Low.
OP0
X
O
Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can
be deactivated automatically on receive or transmit.
OP1
X
O
Output 1: General purpose output or Channel B request to send (RTSBN, active-Low). Can
be deactivated automatically on receive or transmit.
OP2
X
O
Output 2: General purpose output or Channel A transmitter 1X or 16X clock output, or Chan-
nel A receiver 1X clock output.
OP3
X
O
Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel
B transmitter 1X clock output, or Channel B receiver 1X clock output.
OP4
X
O
Output 4: General purpose output or Channel A open-drain, active-Low, RxRDYA/FFULLA
output.
OP5
X
O
Output 5: General purpose output or Channel B open-drain, active-Low, RxRDYB/FFULLB
output.
OP6
X
O
Output 6: General purpose output or Channel A open-drain, active-Low, TxRDYA output.
OP7
X
O
Output 7: General purpose output or Channel B open-drain, active-Low, TxRDYB output.
IP0
X
I
Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN). Pin
has an internal VCC pull-up device supplying 1 to 4 mA of current.
IP1
X
I
Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN). Pin
has an internal VCC pull-up device supplying 1 to 4 mA of current.
IP2
X
I
Input 2: General purpose input or counter/timer external clock input. Pin has an internal VCC
pull-up device supplying 1 to 4
mA of current.
IP3
X
I
Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When
the external clock is used by the transmitter, the transmitted data is clocked on the falling
edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 mA of current.
IP4
X
I
Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the
external clock is used by the receiver, the received data is sampled on the rising edge of the
clock. Pin has an internal VCC pull-up device supplying 1 to 4 mA of current.
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