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參數(shù)資料
| 型號(hào)： | 933669020652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 51K |
| 代理商： | 933669020652 |
December 1990
6
Philips Semiconductors
Product specication
Dual JK ip-op with reset; negative-edge trigger
74HC/HCT107
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
Note to HCT types
The value of additional quiescent supply current (
ICC) for a unit load of 1 is given in the family specifications.
To determine
ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tf = tf = 6 ns; CL = 50 pF
INPUT
UNIT LOAD COEFFICIENT
nK
nR
nCP, nJ
0.60
0.65
1.00
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
VCC
(V)
WAVEFORMS
+25
40 to +85 40 to +125
min.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
nCP to nQ
19
36
45
54
ns
4.5
Fig.6
tPHL/ tPLH
propagation delay
nCP to nQ
21
36
45
54
ns
4.5
Fig.6
tPHL/ tPLH
propagation delay
nR to nQ, nQ
20
38
48
57
ns
4.5
Fig.7
tTHL/ tTLH
output transition time
7
15
19
22
ns
4.5
Fig.6
tW
clock pulse width
HIGH or LOW
16
9
20
24
ns
4.5
Fig.6
tW
reset pulse width
LOW
20
11
25
30
ns
4.5
Fig.7
trem
removal time
nR to nCP
14
8
18
21
ns
4.5
Fig.7
tsu
set-up time
nJ, nK to nCP
20
7
25
30
ns
4.5
Fig.6
th
hold time
nJ, nK to nCP
5
2
5
ns
4.5
Fig.6
fmax
maximum clock pulse
frequency
30
66
24
20
MHz
4.5
Fig.6
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