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參數(shù)資料
| 型號(hào)： | 933669020652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁(yè)數(shù)： | 5/7頁(yè) |
| 文件大?。?/td> | 51K |
| 代理商： | 933669020652 |
December 1990
5
Philips Semiconductors
Product specication
Dual JK ip-op with reset; negative-edge trigger
74HC/HCT107
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
SYMBOL
PARAMETER
Tamb (°C)
TEST CONDITIONS
74HC
UNIT
VCC
(V)
WAVEFORMS
+25
40 to +85 40 to +125
min.
typ.
max. min.
max.
min.
max.
tPHL/ tPLH
propagation delay
nCP to nQ
52
19
15
160
32
27
200
40
34
240
48
41
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
nCP to nQ
52
19
15
160
32
27
200
40
34
240
48
41
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
nR to nQ, nQ
52
19
15
155
31
26
195
39
33
235
47
40
ns
2.0
4.5
6.0
Fig.7
tTHL/ tTLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.6
tW
clock pulse width
HIGH or LOW
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
tW
reset pulse width
LOW
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.7
trem
removal time
nR to nCP
60
12
10
19
7
6
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.7
tsu
set-up time
nJ, nK to nCP
100
20
17
22
8
6
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.6
th
hold time
nJ, nK to nCP
3
6
2
3
ns
2.0
4.5
6.0
Fig.6
fmax
maximum clock pulse
frequency
6.0
30
35
23
70
85
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.6
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