參數(shù)資料
型號(hào)： 932S890CKLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC72
封裝： ROHS COMPLIANT, MLF-72
文件頁數(shù)： 6/21頁
文件大?。?/td> 223K
代理商： 932S890CKLFT
932S890C
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS
IDT
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS
14
932S890C
REV D 052011
SMBus Table: N-Step Select and SIO Readback Register
Byte
5
Name
Control Function
Type
0
1
Default
Bit 7
SIO_SEL
Selects 24MHz or 48MHz
R
24MHz
48MHz
Latch
Bit 6
CPU M/N En
CPU PLL M/N Prog. Enable
R W
M/N Prog. Disabled
M/N Prog. Enabled
0
Bit 5
SRC M/N En
SR C M/N Prog.Enable
R W
M/N Prog. Disabled
M/N Prog. Enabled
0
Bit 4
Test_Sel
Selects Test Mode
RW
N ormal mode
All ouputs are REF/N
0
Bit 3
0
Bit 2
IO_VOUT2
IO Output Voltage Select
(Most Significant Bit)
RW
1
Bit 1
IO_VOUT1
IO Output Voltage Select
RW
0
Bit 0
IO_VOUT0
IO Output Voltage Select
(Least Significant Bit)
RW
1
SMBus Table: Byte Count Register
Byte
6
Name
Control Function
Type
0
1
Default
Bit 7
0
Bit 6
0
Bit 5
BC5
Byte Count bit 5 (MSB)
R W
0
Bit 4
BC4
Byte Count bit 4
R W
0
Bit 3
BC3
Byte Count bit 3
R W
1
Bit 2
BC2
Byte Count bit 2
R W
0
Bit 1
BC1
Byte Count bit 1
R W
0
Bit 0
BC0
Byte Count bit 0 (LSB)
R W
0
SMBus Table: Device ID register
Byte
7
Name
Control Function
Type
0
1
Default
Bit 7
Device ID 7
R
x
Bit 6
Device ID 6
R
x
Bit 5
Device ID 5
R
x
Bit 4
Device ID 4
R
x
Bit 3
Device ID 3
R
x
Bit 2
Device ID 2
R
x
Bit 1
Device ID 1
R
x
Bit 0
Device ID 0
R
x
SMBus Table: Vendor & Revision ID Register
Byte
8
Name
Control Function
Type
0
1
Default
Bit 7
RID3
R
x
Bit 6
RID2
R
x
Bit 5
RID1
R
x
Bit 4
RID0
R
x
Bit 3
VID 3
R
--
0
Bit 2
VID 2
R
--
0
Bit 1
VID 1
R
--
0
Bit 0
VID 0
R
--
1
SMBus Table: WatchDog Timer Control Register
Byte
9
Name
Control Function
Type
0
1
Default
Bit 7
HWD_EN
Watchdog Hard Alarm Enable
R W
Disable and Reload Hartd
Alarm Timer, Clear WD
H ard status bit.
Enable Timer
0
Bit 6
SWD _EN
Watchdog Soft Alarm Enable
R W
D isable
Enable
0
Bit 5
WD Hard Status
WD Hard Alarm Status
R
Normal
Alarm
X
Bit 4
WD Soft Status
WD Soft Alarm Status
R
Normal
Alarm
X
Bit 3
WDTC trl
Watch Dog Alarm Time base
Control
R W
290ms Base
1160ms Base
0
Bit 2
HWD2
WD Hard Alarm Timer Bit 2
R W
1
Bit 1
HWD1
WD Hard Alarm Timer Bit 1
R W
1
Bit 0
HWD0
WD Hard Alarm Timer Bit 0
R W
1
Rev A = 0000
Rev B = 0001
Rev C = 0010
These bits represent the number of Watch Dog Time
Base Units that pass before the Watch Alarm expires.
Default is 7 X 290ms = 2s.
VENDOR ID
REVISION ID
Device ID
89 hex for 932S820
Determines the number of bytes that are read back
from the device. Default is 08 hex.
Reserved
See Table 2: V_IO Selection
(Default is 0.8V)
相關(guān)PDF資料
PDF描述
0550660000 120 A, MODULAR TERMINAL BLOCK, 1 ROW, 1 DECK
9330-10375 POWER/SIGNAL RELAY, DPDT, MOMENTARY, 10A (CONTACT), 28VDC (CONTACT), PANEL MOUNT
9330-4026 POWER/SIGNAL RELAY, DPDT, MOMENTARY, 0.175A (COIL), 28VDC (COIL), 4900mW (COIL), 10A (CONTACT), 28VDC (CONTACT), PANEL MOUNT
9330-4027 POWER/SIGNAL RELAY, DPDT, MOMENTARY, 10A (CONTACT), 28VDC (CONTACT), PANEL MOUNT
9330-10374 POWER/SIGNAL RELAY, DPDT, MOMENTARY, 0.175A (COIL), 28VDC (COIL), 4900mW (COIL), 10A (CONTACT), 28VDC (CONTACT), PANEL MOUNT
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