參數(shù)資料
型號(hào)： 932S890CKLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC72
封裝： ROHS COMPLIANT, MLF-72
文件頁數(shù)： 19/21頁
文件大小： 223K
代理商： 932S890CKLFT
932S890C
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS
IDT
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS
7
932S890C
REV D 052011
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 932S890C. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Electrical Characteristics–Input/Supply/Common Output Parameters
PARA METER
SY MBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
3.3V Core Supply Voltage
VDDxxx
-3.3
GND + 3.9V
V
1
Storage Temperature
Ts
-
-65
15 0
° C
1
A mbient Operating Temp
Tambient
-
070
°C
1
Case Temperature
Tcase
-
11 5
°C
1
Input ESD protection HBM
ESD prot
-
2000
V
1
1Guaranteed by design and characterization, not 100% tested in production.
PARA METER
SY MBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
Notes
3.3V Core Supply Voltage
VDDxxx
-
3.135
3.3
3.465
V
1
Input High Voltage
VIH
VDD = 3.3 V +/-5%
2
VDD + 0.3
V
1
Input Low Voltage
V
IL
VDD = 3.3 V +/-5%
V
SS - 0.3
0.8
V
1
Input High Curren t
IIH
VIN = VDD
-5
5
uA
1
I
IL1
V
IN = 0 V; Inputs with no pull-up
resistors
-5
uA
1
IIL2
V
IN = 0 V; Inputs with pull-up
resistors
-200
uA
1
Operating Current
I
DD3 .3 OP
all outputs driven
25 0
mA
1
Input Frequency
Fi
VDD = 3.3 V +/-5%
14.31818
MHz
2
Pin Inductance
Lpin
7nH
1
C
IN
Logic Inputs
5
pF
1
C
OUT
Outpu t pin capacitance
6
pF
1
CINX
X1 & X2 pins
5
pF
1
Clk S tabilization
TSTAB
From VDD Power-Up to 1st clock
1.8
ms
1
Modulation Frequency
Triangular Modulation
30
33
kHz
1
SMBus Voltage
V DDSMB
2.7
5.5
V
1
Low-level Output Voltage
V
OLSMB
@ I
PUL LUP
0.4
V
1
Current sinking at
V
OL = 0.4 V
I
PU LL UPSMB
46
mA
1
SMBCLK/SMBDA T
Clock/Data Rise Ti me
TRSMB
(Max V IL - 0.15) to
(Min VIH + 0.15 )
1000
ns
1
SMBCLK/SMBDA T
Cl ock/Data Fall Time
TFSMB
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
1
*TA = 0 - 70°C; S upply Voltage VDD = 3.3 V +/-5%
1Guaranteed by desig n and characterization, not 100% tested in production.
Input Low Current
Input Capacitance
2 Input frequ ency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
相關(guān)PDF資料
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