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參數(shù)資料
| 型號： | 932S890CKLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC72 |
| 封裝： | ROHS COMPLIANT, MLF-72 |
| 文件頁數(shù)： | 21/21頁 |
| 文件大小： | 223K |
| 代理商： | 932S890CKLFT |
932S890C
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS
IDT
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS
9
932S890C
REV D 052011
AC Electrical Characteristics–Low-Power DIF Outputs: SRC, SATA
PARA METER
SY MBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SRC/S ATA Frequency
fSRC_SATA
Spread Specturm Off
100
MHz
1,6
Long Term Accuracy
p pm
Spread Specturm Off
-50
+50
ppm
1,6
Rising Edge Slew Rate
t
SLR
Differential Measurement
2.5
8
V/ns
1,2
Falling Edge Slew Rate
t
FLR
Differential Measurement
2.5
8
V/ns
1,2
Slew Rate Variation
t
SLVAR
Single-ended Measurement
20
%
1
Maximum Output Voltage
VHIGH
Include s overshoot
1150
mV
1
Minimum Output Voltage
V LOW
Includes undershoot
-300
mV
1
Differential Voltage S wing
V
SWING
Differential Measurement
300
mV
1
Crossing Point Voltage
V
XABS
Single-ended Measurement
300
55 0
mV
1,3,4
Crossing Point Variation
VXABSVAR
Single-ended Measurement
14 0
mV
1,3,5
Duty Cycle
DCYC
Differential Measurement
45
55
%
1
Jitter - Cycle to Cycle
S RCJC2C
Differential Measurement
12 5
ps
1
SRC[13:0] Skew Even Outputs
SRC
SKEW_E
Differential Measurement
20 0
ps
1,8
SRC[13:0] Skew Odd Outputs
SRC
SKEW_O
Differential Measurement
20 0
ps
1,8
SRC[13:0] Even to Odd Skew
SRC
SKEW
Differential Measurement
1275
1375
1475
ps
1,8
P CIe Gen 1 specs
(1.5 - 22 MHz)
40
86
ps
1, 7
PCIe Gen 2 (8-16 MHz, 5-16 MHz)
Lo-band conten t
(10kHz to 1.5MHz)
1.6
3
ps rms
1, 7
PCIe Gen 2 (8-16 MHz, 5-16 MHz)
Hi-band content
(1.5MHz to Nyquist)
2.6
3.1
ps rms
1, 7
1Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through Vswing centered around differential zero
3 Vxabs is defined as the voltage where CLK = CLK#
4 Only applies to the differential rising edge (CLK rising and CLK# falling)
6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
Jitter, Phase
tjphaseSRC
5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of
CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets
CLK#.
7 Applicable to all SRC outputs. See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not
tested in production.
8 SRC outputs are divided into two banks, odd and even. The odd bank skew window is 200 ps. The even bank skew window is
200ps. The skew between the even and o dd banks is intentionally set at 1375ps.
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