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參數(shù)資料
| 型號： | 89TTM553BL |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Traffic Manager Co-processor |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA960 |
| 封裝： | 35 X 35 MM, 1 MM PITCH, FPBGA-960 |
| 文件頁數(shù)： | 9/30頁 |
| 文件大?。?/td> | 185K |
| 代理商： | 89TTM553BL |
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9 of 30
March 3, 2005
IDT 89TTM553
S ignal Name
I/O Type
Dir.
Freq.
Remarks
IDDQ
3.3V,
internal pulldown
I
N/A
IDDQ input (active high).
For IDT use only. Do not connect.
RESERVE_1
3.3V LVTTL,
4 mA drive
O
N/A
For IDT use only. Do not connect.
SCAN_EN
3.3V
I
N/A
Scan enable (active high)
For IDT use only.
Attach to a 4.7K resistor to 0V
RESERVE_0
3.3V,
internal pullup
I
N/A
Tristate enable (active low)
For IDT use only.
Attach to a 4.7K resistor to 3.3V
TCK
3.3V
I
—
JTAG (IEEE 1149.1) clock input.
TDI
3.3V,
internal pullup
I
—
JTAG (IEEE 1149.1) test data input.
TDO
3.3V LVTTL,
12 mA drive
O
—
JTAG (IEEE 1149.1) test data output.
TMS
3.3V,
internal pullup
I
—
JTAG (IEEE 1149.1) test mode select
TRST_N
3.3V,
internal pullup
I
—
JTAG (IEEE 1149.1) test reset input.
Table 10 Test I/O
S ignal Name
I/O Type
Dir.
Freq.
Remarks
PLL_2X_BPCLK
3.3V,
internal pulldown
I
N/A
Bypass Clock Input
For IDT use only. Do not connect.
PLL_BP_MODE
3.3V,
internal pulldown
I
N/A
Bypass Clock Input
For IDT use only. Do not connect.
PLL_MON
3.3V LVTTL,
12mA drive
O
N/A
PLL Monitor
For IDT use only. Do not connect.
PLL_CFG_OVR
3.3V,
internal pulldown
I
N/A
PLL Configuration Override
PLL_RST
3.3V
I
Async
PLL reset. A special initialization sequence is required.
PLL_VDDA
1.8V
—
—
PLL Analog VDD
PLL_VSSA
—
—
—
PLL Analog VSS
PLL_SYS_REFCLK
3.3V
I
100 MHz
Chip core PLL reference clock.
RESET_N
3.3V,
internal pullup
I
Async
Chip reset input (active low).
VDD18
—
—
—
1.8V core power
VDD15
—
—
—
1.5V I/O power for HSTL-2 I/Os: Isolated output buffer supply
set nomnally to 1.5V
Table 11 PLL I/O (Part 1 of 2)
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