參數(shù)資料
型號(hào)： 89TTM553BL
廠(chǎng)商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 微控制器/微處理器
英文描述： Traffic Manager Co-processor
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA960
封裝： 35 X 35 MM, 1 MM PITCH, FPBGA-960
文件頁(yè)數(shù)： 5/30頁(yè)
文件大?。?/td> 185K
代理商： 89TTM553BL
5 of 30
March 3, 2005
IDT 89TTM553
BXT_WR_N
1.5V HSTL Class 1
O
175 MHz
BXT QDR SRAM synchronous write output (active low): When
asserted, a write cycle is initiated to the external QDR SRAM
devices.
BXT_DOUT[3:0]
1.5V HSTL Class 1
O
175 MHz
BXT QDR SRAMwrite data outputs: Output data is synchro-
nized to the K and K# during write operations
BXT_LLT_VREF
0.75V
—
—
HSTL reference. Nomnally V
DDQ
/ 2, so connect to 0.75V
S ignal Name
I/O Type
Dir.
Freq.
Remarks
FCT_CLK_CP,
FCT_CLK_CN
1.5V HSTL Class 1
I
175 MHz
FCT QDR SRAM input clock: This clock pair registers data
inputs on the rising edge of C and C# All synchronous inputs
must meet setup and hold times around the clock rising
edges.
FCT_CLK_KP,
FCT_CLK_KN
1.5V HSTL Class 1
O
175 MHz
FCT QDR SRAM output clock: This clock pair times the con-
trol outputs to the rising edge of K, and times the address and
data outputs to the rising edge of K and K#.
FCT_ADDR[19:0]
1.5V HSTL Class 1
O
175 MHz
FCT QDR SRAM address outputs.
FCT_RD_N
1.5V HSTL Class 1
O
175 MHz
FCT QDR SRAMsynchronous read output (active low): When
asserted, a read cycle is initiated to the external QDR SRAM
devices.
FCT_DIN[27:0]
1.5V HSTL Class 1
I
175 MHz
FCT QDR SRAM data inputs: Input data must meet setup and
hold times around the rising edges of C and C#during read
operations
FCT_WR_N
1.5V HSTL Class 1
O
175 MHz
FCT QDR SRAMsynchronous write output (active low): When
asserted, a write cycle is initiated to the external QDR SRAM
devices.
FCT_DOUT[27:0]
1.5V HSTL Class 1
O
175 MHz
FCT QDR SRAM write data outputs: Output data is synchro-
nized to the K and K# during write operations
FCT_VREF[1:0]
0.75
—
—
HSTL reference. Nomnally V
DDQ
/ 2, so connect to 0.75V
Table 3 Flow Control Table QDR SRAM
S ignal Name
I/O Type
Dir.
Freq.
Remarks
FPT_CLK_CP,
FPT_CLK_CN
1.5V HSTL Class 1
I
175 MHz
FPT QDR SRAMinput clock: This clock pair registers data
inputs on the rising edge of C and C# All synchronous inputs
must meet setup and hold times around the clock rising
edges.
FPT_CLK_KP,
FPT_CLK_KN
1.5V HSTL Class 1
O
175 MHz
FPT QDR SRAMoutput clock: This clock pair times the con-
trol outputs to the rising edge of K, and times the address and
data outputs to the rising edge of K and K#.
FPT_ADDR[20:0]
1.5V HSTL Class 1
O
175 MHz
FPT QDR SRAMaddress outputs.
FPT_RD_N
1.5V HSTL Class 1
O
175 MHz
FPT QDR SRAMsynchronous read output (active low): When
asserted, a read cycle is initiated to the external QDR SRAM
devices.
Table 4 Flow Parameters Table QDR SRAM (Part 1 of 2)
S ignal Name
I/O Type
Dir.
Freq.
Remarks
Table 2 Buffer Linked List Extension QDR SRAM (Part 2 of 2)
相關(guān)PDF資料
PDF描述
8A05 CURRENT 8.0 Amperes VOLTAGE 50 TO 100 VOLTS
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8A20 CURRENT 8.0 Amperes VOLTAGE 50 TO 100 VOLTS
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