參數(shù)資料
型號(hào): 89TTM553BL
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: Traffic Manager Co-processor
中文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA960
封裝: 35 X 35 MM, 1 MM PITCH, FPBGA-960
文件頁數(shù): 6/30頁
文件大?。?/td> 185K
代理商: 89TTM553BL
6 of 30
March 3, 2005
IDT 89TTM553
FPT_DIN[35:0]
1.5V HSTL Class 1
I
175 MHz
FPT QDR SRAMdata inputs: Input data must meet setup and
hold times around the rising edges of C and C#during read
operations
FPT_WR_N
1.5V HSTL Class 1
O
175 MHz
FPT QDR SRAMsynchronous write output (active low): When
asserted, a write cycle is initiated to the external QDR SRAM
devices.
FPT_BW_N[3:0]
1.5V HSTL Class 1
O
175 MHz
FPT QDR SRAMsynchronous write byte enables (active low)
FPT_DOUT[35:0]
1.5V HSTL Class 1
O
175 MHz
FPT QDR SRAMwrite data outputs: Output data is synchro-
nized to the K and K# during write operations
FPT_VREF[1:0]
0.75V
HSTL reference. Nomnally V
DDQ
/ 2, so connect to 0.75V
S ignal Name
I/O Type
Dir.
Freq.
Remarks
GPT_CLK_CP,
GPT_CLK_CN
1.5V HSTL Class 1
I
175 MHz
GPT QDR SRAM input clock: This clock pair registers data
inputs on the rising edge of C and C# All synchronous inputs
must meet setup and hold times around the clock rising
edges.
GPT_CLK_KP,
GPT_CLK_KN
1.5V HSTL Class 1
O
175 MHz
GPT QDR SRAM output clock: This clock pair times the con-
trol outputs to the rising edge of K, and times the address and
data outputs to the rising edge of K and K#.
GPT_ADDR[20:0]
1.5V HSTL Class 1
O
175 MHz
GPT QDR SRAM address outputs.
GPT_RD_N
1.5V HSTL Class 1
O
175 MHz
GPT QDR SRAMsynchronous read output (active low): When
asserted, a read cycle is initiated to the external QDR SRAM
devices.
GPT_DIN[17:0]
1.5V HSTL Class 1
I
175 MHz
GPT QDR SRAMdata inputs: Input data must meet setup and
hold times around the rising edges of C and C#during read
operations.
GPT_WR_N
1.5V HSTL Class 1
O
175 MHz
GPT QDR SRAMsynchronous write output (active low): When
asserted, a write cycle is initiated to the external QDR SRAM
devices.
GPT_BW_N[1:0]
1.5V HSTL Class 1
O
175 MHz
GPT QDR SRAM synchronous byte enables (active low).
GPT_DOUT[17:0]
1.5V HSTL Class 1
O
175 MHz
GPT QDR SRAM write data outputs: Output data is synchro-
nized to the K and K# during write operations.
GPT_VREF
0.75V
HSTL reference. Nomnally V
DDQ
/ 2, so connect to 0.75V
Table 5 Group Parameters Table QDR SRAM
S ignal Name
I/O Type
Dir.
Freq.
Remarks
Table 4 Flow Parameters Table QDR SRAM (Part 2 of 2)
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