參數(shù)資料
型號(hào)： 87L51FB
廠商： NXP Semiconductors N.V.
英文描述： CMOS single-chip 3.0V 8-bit microcontrollers
中文描述： CMOS單芯片3.0V 8位微控制器
文件頁(yè)數(shù)： 8/16頁(yè)
文件大小： 187K
代理商： 87L51FB
Philips Semiconductors
Product specification
87L51FA/87L51FB
CMOS single-chip 3.0V 8-bit microcontrollers
1996 Aug 16
3-157
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0
°
C to +70
°
C, –40 to +85
°
C, V
CC
= 3.0V to 4.5V, V
SS
= 0V
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
1
MAX
UNIT
V
IL
Input low voltage, except EA
2,3
–0.5
0.8
V
V
IL1
Input low voltage to EA
2,3
0
0.8
V
V
IH
Input high voltage, except XTAL1, RST
2,4
2.0
V
CC
+0.5
V
V
IH1
Input high voltage, XTAL1, RST
2,4
0.7V
CC
V
CC
+0.5
V
V
OL
Output low voltage, ports 1, 2, 3
5
I
OL
= 1.6mA
6
I
OL
= 3.2mA
6
0.45
V
V
OL1
Output low voltage, port 0, ALE, PSEN
5
0.45
V
V
OH
Output high voltage, ports 1, 2, 3, ALE, PSEN
7
I
OH
= –20
μ
A
V
CC
– 0.5
V
V
OH1
Output high voltage (port 0 in external bus mode),
ALE
8
, PSEN
7
I
OH
= –3.2mA
V
CC
– 0.7
V
I
IL
Logical 0 input current, ports 1, 2, 3
2
V
IN
= 0.4V
–50
μ
A
I
TL
Logical 1-to-0 transition current, ports 1, 2, 3
2
See note 9
–650
μ
A
I
LI
Input leakage current, port 0
0.45 V
IN
< V
CC
– 0.3
±
10
μ
A
I
CC
Power supply current:2
Active mode @ 20MHz
10
Idle mode @ 20MHz
Power-down mode
See note 11
9
2
10
22
6
75
mA
mA
μ
A
R
RST
Internal reset pull-down resistor
40
225
k
C
IO
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 3.3V.
2. These values apply only to T
amb
= 0
°
C to +70
°
C.
3. For V
CC
voltages above 3.6V and less than 5.5V, V
IL
= 0.3V
CC
– 0.1
4. For V
CC
voltages above 3.6V and less than 5.5V, V
IH
= 0.3V
CC
+ 0.92
5. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin:
15mA (*NOTE: This is 85
°
C specification.)
Maximum I
OL
per 8-bit port:
26mA
Maximum total I
for all outputs:
71mA
If I
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
6. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
s of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
OL
can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
7. Capacitive loading on ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the 0.9V
CC
specification when the
address bits are stabilizing.
8. ALE is tested to V
OH1
, except when ALE is off then V
OH
is the voltage specification.
9. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V
IN
is approximately 1.5V.
10.I
CCMAX
at other frequencies is given by: Active mode: I
CCMAX
= 0.8
×
FREQ + 6: Idle mode: I
CCMAX
= 0.19
×
FREQ +2.50,
where FREQ is the external oscillator frequency in MHz. I
CCMAX
is given in mA. See Figure 8.
11. See Figures 9 through 12 for I
CC
test conditions.
12.Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA is 25pF). These values are
guaranteed by design and are not tested.
Pin capacitance
12
(except EA)
15
pF
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