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參數資料
| 型號： | 87L51FB |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | CMOS single-chip 3.0V 8-bit microcontrollers |
| 中文描述： | CMOS單芯片3.0V 8位微控制器 |
| 文件頁數： | 5/16頁 |
| 文件大?。?/td> | 187K |
| 代理商： | 87L51FB |
Philips Semiconductors
Product specification
87L51FA/87L51FB
CMOS single-chip 3.0V 8-bit microcontrollers
1996 Aug 16
3-154
PIN DESCRIPTIONS
(Continued)
PIN NUMBER
DIP
LCC
MNEMONIC
QFP
TYPE
NAME AND FUNCTION
P3.0–P3.7
10–17
11,
13–19
5,
7–13
I/O
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 3 pins that are externally being pulled low will source current because of the pull-ups.
(See DC Electrical Characteristics: I
IL
). Port 3 also serves the special features of the 80C51
family, as listed below:
RxD (P3.0):
Serial input port
TxD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt
INT1 (P3.3):
External interrupt
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
Reset:
A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V
SS
permits a power-on reset using only an external
capacitor to V
CC
.
Address Latch Enable/Program Pulse:
Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.
Note that one ALE pulse is skipped during each access to external data memory. This pin is
also the program pulse input (PROG) during EPROM programming.
Program Store Enable:
The read strobe to external program memory. When the
87L51FA/FB is executing code from the external program memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program memory.
External Access Enable/Programming Supply Voltage:
EA must be externally held low
to enable the device to fetch code from external program memory locations 0000H and
1FFFH. If EA is held high, the device executes from internal program memory unless the
program counter contains an address greater than 1FFFH. This pin also receives the
12.75V programming supply voltage (V
PP
) during EPROM programming. If security bit 1 is
programmed, EA will be internally latched on Reset.
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
Crystal 2:
Output from the inverting oscillator amplifier.
10
11
12
13
14
15
16
17
9
11
13
14
15
16
17
18
19
10
5
7
8
9
10
11
12
13
4
I
O
I
I
I
I
O
O
I
RST
ALE/PROG
30
33
27
I/O
PSEN
29
32
26
O
EA/V
PP
31
35
29
I
XTAL1
19
21
15
I
XTAL2
18
20
14
O
NOTE:
To avoid “l(fā)atch-up” effect at power-on, the voltage on any pin at any time must not be higher than V
CC
+ 0.5V or V
SS
– 0.5V, respectively.
TIMER 2
This is a 16-bit up or down counter, which can be operated as either
a timer or event counter. It can be operated in one of three different
modes (autoreload, capture or as the baud rate generator for the
UART).
In the autoreload mode the Timer can be set to count up or down by
setting or clearing the bit DCEN in the T2CON Special Function
Register. The SFR’s RCAP2H and RCAP2L are used to reload the
Timer upon overflow or a 1-to-0 transition on the T2EX input (P1.1).
In the Capture mode Timer 2 can either set TF2 and generate an
interrupt or capture its value. To capture Timer 2 in response to a
1-to-0 transition on the T2EX input, the EXEN2 bit in the T2CON
must be set. Timer 2 is then captured in SFR’s RCAP2H and
RCAP2L.
As the baud rate generator, Timer 2 is selected by setting TCLK
and/or RCLK in T2CON. As the baud rate generator Timer 2 is
incremented at
1
/
2
the oscillator frequency.
ENHANCED UART
The 87L51FA/FB UART has all of the capabilities of the standard
80C51 UART plus Framing Error Detection and Automatic Address
Recognition. As in the 80C51, all four modes of operation are
supported as well as the 9th bit in modes 2 and 3 that can be used
to facilitate multiprocessor communication.
The Framing Error Detection allows the UART to look for missing
stop bits. If a Stop bit is missing, the FE bit in the SCON SFR is set.
The FE bit can be checked after each transmission to detect
communication errors. The FE bit can only be cleared by software
and is not affected by a valid stop bit.
Automatic Address Recognition is used to reduce the CPU service
time for the serial port. The CPU only needs to service the UART
when it is addressed and, with this done by the on-chip circuitry, the
need for software overhead is greatly reduced. This mode works
similar to the 9-bit communication mode, except that it uses only 8
bits and the Stop bit is used to cause the RI bit to be set. There are
two SFRs associated with this mode. They are SADDR, which holds
the slave address and SADEN, which contains a mask that allows
selective masking of the slave address so that broadcast addresses
can be used.
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