參數(shù)資料
型號(hào)： 87C554
廠商： NXP Semiconductors N.V.
英文描述： 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
中文描述： 80C51的8位微控制器。 6小時(shí)運(yùn)作16K/512檢察官辦公室/光盤(pán)/無(wú)ROM，7通道10位A / D，I2C和脈寬調(diào)制，捕捉/比較，高I / O，64L LQFP封裝
文件頁(yè)數(shù)： 66/76頁(yè)
文件大?。?/td> 400K
代理商： 87C554
Philips Semiconductors
Preliminary specification
80C554/83C554/87C554
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I
2
C, PWM,
capture/compare, high I/O, 64L LQFP
2000 Nov 10
66
AC ELECTRICAL CHARACTERISTICS
V
DD
and T
amb
minimum and maximum, per device specifications table; V
SS
= 0 V; C
L
= 100 pF for Port 0, ALE and PSEN; C
L
= 80 pF for all
other outputs unless otherwise specified.
16 MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
External Program Memory
1/f
CLK
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
External Data Memory
49
System clock frequency, see Note 1
3.5
16
MHz
49
ALE pulse width
37.5
–
t
CLK
–25
0.5 t
CLK
–25
0.5 t
CLK
–25
–
–
ns
49
Address valid to ALE LOW
6.25
–
–
ns
49
Address hold after ALE LOW
6.25
–
–
ns
49
ALE LOW to valid instruction in
–
60
2 t
CLK
–65
–
ns
49
ALE LOW to PSEN LOW
6.25
–
0.5 t
CLK
–25
1.5 t
CLK
–45
–
ns
49
PSEN pulse width
48.75
–
–
ns
49
PSEN LOW to valid instruction in
–
33.75
1.5 t
CLK
–60
–
ns
49
Input instruction hold after PSEN
0
–
0
ns
49
Input instruction float after PSEN
–
6.25
–
0.5 t
CLK
–25
2.5 t
CLK
–80
10
ns
49
Address to valid instruction in
–
76.25
–
ns
49
PSEN LOW to address float
–
10
–
ns
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
WHQX
t
QVWH
t
RLAZ
t
WHLH
External Clock
50, 51
RD pulse width
87.5
–
3 t
CLK
–100
3 t
CLK
–100
–
–
ns
50, 51
WR pulse width
87.5
–
–
ns
50, 51
RD LOW to valid data in
–
66.25
2.5 t
CLK
–90
–
ns
50, 51
Data hold after RD
0
–
0
ns
50, 51
Data float after RD
–
42.5
–
t
CLK
–20
4 t
CLK
–150
4.5 t
CLK
–165
1.5 t
CLK
+50
–
ns
50, 51
ALE LOW to valid data in
–
100
–
ns
50, 51
Address to valid data in
–
116.25
–
ns
50, 51
ALE LOW to RD or WR LOW
43.75
143.75
1.5 t
CLK
–50
2 t
CLK
–75
0.5 t
CLK
–30
0.5 t
CLK
–25
3.5 t
CLK
–130
–
ns
50, 51
Address valid to RD low or WR LOW
50
–
ns
50, 51
Data valid to WR transition
1.25
–
–
ns
51
Data hold after WR
6.25
–
–
ns
50, 51
Data valid time WR HIGH
88.75
–
–
ns
50, 51
RD LOW to address float
–
0
0
ns
50, 51
RD or WR HIGH to ALE HIGH
6.25
56.25
0.5 t
CLK
–25
0.5 t
CLK
+25
ns
t
CHCX
t
CLCX
t
CLCH
t
CHCL
UART Timing – Shift Register Mode
52
High time
33.3
50
t
CLK
t
CLK
0.4
t
CLK
t
CLK
0.6
ns
52
Low time
33.3
50
0.4
0.6
ns
52
Rise time
–
20
–
20
ns
52
Fall time
–
20
–
20
ns
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
53
Serial port clock cycle time
500
–
6 t
CLK
5 t
CLK
–133
t
CLK
–30
0
–
ns
53
Output data setup to clock rising edge
179.5
–
–
ns
53
Output data hold after clock rising edge
32.5
–
–
ns
53
Input data hold after clock rising edge
0
–
–
ns
53
Clock rising edge to input data valid
–
179.5
–
5 t
CLK
–133
ns
相關(guān)PDF資料
PDF描述
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