參數(shù)資料
型號(hào)： 87C554
廠商： NXP Semiconductors N.V.
英文描述： 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
中文描述： 80C51的8位微控制器。 6小時(shí)運(yùn)作16K/512檢察官辦公室/光盤/無(wú)ROM，7通道10位A / D，I2C和脈寬調(diào)制，捕捉/比較，高I / O，64L LQFP封裝
文件頁(yè)數(shù)： 27/76頁(yè)
文件大小： 400K
代理商： 87C554
Philips Semiconductors
Preliminary specification
80C554/83C554/87C554
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I
2
C, PWM,
capture/compare, high I/O, 64L LQFP
2000 Nov 10
27
10-Bit ADC Resolution and Analog Supply:
Figure 24 shows how
the ADC is realized. The ADC has its own supply pins (AV
DD
and
AV
SS
) and two pins (Vref+ and Vref–) connected to each end of the
DAC’s resistance-ladder. The ladder has 1023 equally spaced taps,
separated by a resistance of “R”. The first tap is located 0.5 x R
above Vref–, and the last tap is located 1.5 x R below Vref+. This
gives a total ladder resistance of 1024 x R. This structure ensures
that the DAC is monotonic and results in a symmetrical quantization
error as shown in Figure 26.
For input voltages between Vref– and (Vref–) + 1/2 LSB, the 10-bit
result of an A/D conversion will be 00 0000 0000B = 000H. For input
voltages between (Vref+) – 3/2 LSB and Vref+, the result of a
conversion will be 11 1111 1111B = 3FFH. AVref+ and AVref– may
be between AV
DD
+ 0.2 V and AV
SS
– 0.2 V. AVref+ should be
positive with respect to AVref–, and the input voltage (Vin) should be
between AVref+ and AVref–. If the analog input voltage range is from
2 V to 4 V, then 10-bit resolution can be obtained over this range if
AVref+ = 4 V and AVref– = 2 V.
The result can always be calculated from the following formula:
Result
1024
V
IN
AV
ref
AV
ref
AV
ref
Power Reduction Modes
The 8xC554 has two reduced power modes of operation: the idle
mode and the power-down mode. These modes are entered by
setting bits in the PCON special function register. When the 8xC554
enters the idle mode, the following functions are disabled:
CPU
Timer T2
PWM0, PWM1
ADC
(halted)
(halted and reset)
(reset; outputs are high)
(may be enabled for operation in Idle mode
by setting bit AIDC (AUXR1.6) ).
In idle mode, the following functions remain active:
Timer 0
Timer 1
Timer T3
SIO0 SIO1
External interrupts
When the 8xC554 enters the power-down mode, the oscillator is
stopped. The power-down mode is entered by setting the PD bit in
the PCON register. The PD bit can only be set if the EW input is tied
HIGH.
SUCCESSIVE
APPROXIMATION
CONTROL LOGIC
SUCCESSIVE
APPROXIMATION
REGISTER
+
–
DECODER
MSB
COMPARATOR
LSB
START
READY
AV
ref+
AV
ref–
R/2
R
R
R
R
R
R/2
TOTAL RESISTANCE
=
1023R + 2 x R/
=
1024R
V
ref
V
in
1023
1022
1021
3
2
1
0
Value 0000 0000 00
Value 1111 1111 11
is output for voltages V
ref–
to (V
ref–
+ 1/2 LSB)
is output for voltages (V
ref+
– 3/2 LSB) to V
ref+
SU00961
Figure 24. ADC Realization
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