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Intel
82865G/82865GV GMCH Datasheet
17
Introduction
1.2
Related Documents
Row Address
The row address is presented to the DRAMs during an Activate command, and indicates
which page to open within the specified bank (the bank number is presented also).
Scalable Bus
Processor-to-GMCH interface. The compatible mode of the Scalable Bus is the P6 Bus. The
enhanced mode of the Scalable Bus is the P6 Bus plus enhancements primarily consisting
of source synchronous transfers for address and data, and FSB interrupt delivery. The
Intel
Pentium
4 processor implements a subset of the enhanced mode.
Single-Sided
DIMM
Terminology often used to describe a DIMM that contains one DRAM row. Usually one row
fits on a single side of the DIMM allowing the backside to be empty.
SDR
Single Data Rate SDRAM.
SDRAM
Synchronous Dynamic Random Access Memory.
Secondary PCI
The physical PCI interface that is a subset of the AGP bus driven directly by the GMCH. It
supports a subset of 32-bit, 66 MHz PCI 2.0 compliant components, but only at 1.5 V
(not 3.3 V or 5 V).
SSTL_2
Stub Series Terminated Logic for 2.6 Volts (DDR)
Document
Document Number/
Location
Intel
865G/865GV/865PE/865P Chipset Platform Design Guide
http://developer.intel.com/
design/chipsets/designex/
252518.htm
Intel
865G/865GV/865PE/865P Chipset Thermal Design Guide
http://developer.intel.com/
design/chipsets/designex/
252519.htm
Intel
865G/865GV/865PE/865P Chipset Schematics
http://developer.intel.com/
design/chipsets/schematics/
252813.htm
Intel
865G/865GV/865PE/865P Chipset CRB Schematics Addendum for
the Intel
Pentium
4 processor on 90 nm Process w/Loadline A Platforms -
2 Phase VR
http://developer.intel.com/
design/chipsets/schematics/
300683.htm
Intel
865G/865GV/865PE/865P Chipset CRB Schematics Addendum for
the Intel
Pentium
4 processor on 90 nm Process w/Loadline A Platforms -
3 Phase VR
http://developer.intel.com/
design/chipsets/schematics/
300684.htm
Intel
82801EB I/O Controller Hub 5 (ICH5) and Intel
82801ER I/O
Controller Hub 5R (ICH5R) Datasheet
http://developer.intel.com/
design/chipsets/specupdt/
252517.htm
Intel
Pentium
4 processor with 512-KB L2 Cache on 0.13 Micron Process
Datasheet
http://developer.intel.com/
design/pentium4/datashts/
298643.htm
Intel
Pentium
4 processor on 90 nm Process Datasheet
http://developer.intel.com/
design/pentium4/datashts/
300561.htm
Intel
Pentium
4 processor on 90 nm Process Thermal and Mechanical
Design Guide
http://developer.intel.com/
design/Pentium4/guides/
300564.htm
JEDEC Double Data Rate (DDR) SDRAM Specification
www.jedec.org
Table 1. General Terminology (Sheet 2 of 2)
Terminology
Description