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148
Intel
82865G/82865GV GMCH Datasheet
Functional Description
When the processor or the GMCH drives data, each 16-bit segment is analyzed. If more than 8 of
the 16 signals would normally be driven low on the bus, the corresponding DINVx# signal will be
asserted and the data will be inverted prior to being driven on the bus. When the processor or the
GMCH receives data, it monitors DINV[3:0]# to determine if the corresponding data segment
should be inverted.
5.1.2
FSB Interrupt Overview
Pentium 4 processors support FSB interrupt delivery. They do
not
support the APIC serial bus
interrupt delivery mechanism. Interrupt related messages are encoded on the FSB as “Interrupt
Message Transactions.” In the 865G chipset platform FSB interrupts may originate from the
processor on the system bus, or from a downstream device on the hub interface, or AGP. In the later
case the GMCH drives the “Interrupt Message Transaction” onto the system bus.
In the 865G chipset environment the ICH5 contains IOxAPICs, and its interrupts are generated as
upstream HI memory writes. Furthermore, PCI 2.3 defines MSIs (Message Signaled Interrupts)
that are also in the form of memory writes. A PCI 2.3 device may generate an interrupt as an MSI
cycle on its PCI bus instead of asserting a hardware signal to the IOxAPIC. The MSI may be
directed to the IOxAPIC which in turn generates an interrupt as an upstream hub interface memory
write. Alternatively, the MSI may be directed directly to the FSB. The target of an MSI is
dependent on the address of the interrupt memory write. The GMCH forwards inbound HI and
AGP/PCI (PCI semantic only) memory writes to address 0FEEx_xxxxh to the FSB as “Interrupt
Message Transactions.”
5.1.2.1
Upstream Interrupt Messages
The GMCH accepts message-based interrupts from PCI (
PCI semantics only
) hub interface and
forwards them to the FSB as Interrupt Message Transactions. The interrupt messages presented to
the GMCH are in the form of memory writes to address 0FEEx_xxxxh. At the HI or PCI interface,
the memory write interrupt message is treated like any other memory write; it is either posted into
the inbound data buffer (if space is available) or retried (if data buffer space is not immediately
available). Once posted, the memory write from PCI or hub interface to address 0FEEx_xxxxh is
decoded as a cycle that needs to be propagated by the GMCH to the FSB as an Interrupt Message
Transaction.