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Intel
82865G/82865GV GMCH Datasheet
125
Register Description
3.8.20
BCTRL3—Bridge Control Register (Device 3)
Address Offset:
Default Value:
Access:
Size:
3Eh
00h
R/W, RO
8 bits
The bit field definitions for VGAEN and MDAP are detailed in
Table 12
.
Bit
Description
7
Fast Back-to-Back Enable (FB2BEN)—RO.
Hardwired to 0. The GMCH does not generate fast
back-to-back cycles as a master on AGP.
6
Secondary Bus reset (SREST)—RO.
Hardwired to 0. The GMCH does not support generation of
reset via this bit on the AGP.
5
Master Abort Mode (MAMODE)—RO.
Hardwired to 0. This means that when acting as a master on
CSA, the GMCH will discard writes and return all 1s during reads when a master abort occurs.
4
Reserved.
3
VGA Enable (VGAEN)—R/W.
This bit control the routing of processor-initiated transactions
targeting VGA compatible I/O and memory address ranges. This bit works in conjunction with the
GMCHCFG[MDAP] bit (Device 0, offset C6h) as described in
Table 12
.
0 = Disable
1 = Enable
2
ISA Enable (ISAEN)—R/W.
This bit modifies the response by the GMCH to an I/O access issued by
the processor that targets ISA I/O addresses. This applies only to I/O addresses that are enabled by
the IOBASE and IOLIMIT registers.
0 = Disable (default). All addresses defined by the IOBASE and IOLIMIT for processor I/O
transactions are mapped to CSA.
1 = Enable. The GMCH does not forward to CSA any I/O transactions addressing the last
768 bytes in each 1-KB block, even if the addresses are within the range defined by the
IOBASE and IOLIMIT registers. Instead of going to CSA, these cycles are forwarded to HI
where they can be subtractively or positively claimed by the ISA bridge.
1
SERR Enable (SERREN)—RO.
Hardwired to 0. This bit normally controls forwarding SERR# on the
secondary interface to the primary interface. However, the GMCH does not support the SERR#
signal on the CSA Bus.
0
Parity Error Response Enable (PEREN)—RO.
Hardwired to 0.
Table 12. VGAEN and MDAP Definitions
VGAEN
MDAP
Description
0
0
All References to MDA and VGA space are routed to HI.
0
1
Illegal combination.
1
0
All VGA references are routed to this bus. MDA references are routed to HI.
1
1
All VGA references are routed to this bus. MDA references are routed to HI.