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參數(shù)資料
| 型號： | 82845Mx |
| 廠商： | Intel Corp. |
| 英文描述： | Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 中文描述： | 英特爾845系列芯片組的手機82845MP/82845MZ芯片組內(nèi)存控制器中樞移動（婦幼保健米） |
| 文件頁數(shù)： | 11/157頁 |
| 文件大?。?/td> | 1407K |
| 代理商： | 82845MX |
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Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
11
R
Terminology
MCH-M
- The Mobile Memory Controller Hub-M component that contains the processor interface,
DRAM controller, and AGP interface. It communicates with the I/O controller hub (ICH3-M) and other
IO controller hubs over proprietary interconnect called the hub interface.
ICH3-M
- The Mobile I/O Controller Hub 3-M component that contains the primary PCI interface, LPC
interface, USB, ATA-100, AC’97, and other IO functions. It communicates with the Intel
845MP/845MZ Chipset MCH-M over a proprietary interconnect called hub interface.
Host
- This term is used synonymously with processor.
Core
- The internal base logic in the MCH-M.
System Bus
- Processor-to-MCH-M interface. The Enhanced Mode of the Scalable Bus is the P6 Bus
plus enhancements, consisting of source synchronous transfers for address and data, and system bus
interrupt delivery. The Mobile Intel Pentium 4 Processor-M implements a subset of Enhanced Mode.
Hub interface
- The proprietary hub interconnect that ties the MCH-M to the ICH3-M. In this document
hub interface cycles originating from or destined for the primary PCI interface on the ICH3-M is
generally referred to as hub interface cycles.
Accelerated Graphics Port (AGP)
- Refers to the AGP interface that is in the MCH-M. It supports
AGP 2.0 compliant components only with 1.5V signaling level. PIPE# and SBA addressing cycles and
their associated data phases are generally referred to as AGP transactions. FRAME# cycles over the AGP
bus are generally referred to as AGP/PCI transactions.
PCI_A
- The physical PCI bus, driven directly by the ICH3-M component. It supports 5-V, 32-bit, 33-
MHz PCI 2.2 compliant components. Communication between PCI_A and MCH-M occurs over hub
interface. Note: Even though it is referred to as PCI_A it is not PCI Bus #0 from a configuration
standpoint.
Full Reset
- A Full MCH-M Reset is defined in this document when RSTIN# is asserted.
System Bus
- Synonymous with Host or Front Side Bus
GART
- Graphics Aperture Re-map Table. This table contains the page re-map information used during
AGP aperture address translations.
GTLB
- Graphics Translation Look-aside Buffer. A cache used to store frequently used GART entries.
UP
– Uniprocessor
DBI
– Dynamic Bus inversion
MSI
– Message Signaled Interrupts. MSI’s allow a device to request interrupt service via a standard
Memory Write transaction instead of through a hardware signal.
IPI
– Inter Processor Interrupt
Word
– 16 bits = 2 bytes
Dword (DW)
– Doubleword: 32bits = 4 bytes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82845MZ | Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 82845PE | 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH) |
| 82845GE | 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH) |
| 8284A | Clock Generator and Driver for 8066, 8088 Processors |
| 8284A-1 | Clock Generator and Driver for 8066, 8088 Processors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82845MZ | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 82845PE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH) |
| 8284611SM | 制造商:Thomas & Betts 功能描述: |
| 828461-2 | 制造商:TE Connectivity 功能描述:19P CPC STECK-GEH - Bulk |
| 828462-1 | 制造商:TE Connectivity 功能描述:19P CPC AUFNAHMEGEH - Bulk |
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