參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 6/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
6
Datasheet
4.3.2.1.
APIC Configuration Space (FEC0_0000h -FECF_FFFFh,
FEE0_0000h- FEEF_FFFFh)........................................................118
High BIOS Area (FFE0_0000h -FFFF_FFFFh) ............................118
System Management Mode (SMM) Memory Range....................................................118
4.4.1.
SMM Space Definition ...............................................................................119
4.4.2.
SMM Space Restrictions ...........................................................................119
4.4.3.
SMM Space Combinations ........................................................................120
4.4.4.
Initialization and Usage of SMRAM and Graphics Local Memory.............120
Memory Shadowing .....................................................................................................120
I/O Address Space.......................................................................................................120
4.6.1.
AGP/PCI - I/O Address Mapping ...............................................................121
GMCH2-M Address Decode Rules and Cross-Bridge Address Mapping....................121
4.7.1.
Address Decode Rules..............................................................................121
4.7.2.
The Hub Interface Accesses to GMCH2-M that Cross Device Boundaries122
4.7.3.
AGP Interface Decode Rules.....................................................................122
4.7.3.1.
Cycles Initiated Using PCI Protocol...............................................122
4.7.3.2.
Cycles Initiated Using AGP Protocol.............................................123
4.7.3.3.
AGP Accesses to GMCH2-M that Cross Device Boundaries.......123
4.7.4.
Legacy VGA Ranges .................................................................................124
Host Interface...............................................................................................................125
4.8.1.
Host Bus Device Support...........................................................................125
4.8.2.
Special Cycles ...........................................................................................127
System Memory DRAM Interface ................................................................................128
4.9.1.
DRAM Organization and Configuration......................................................128
4.9.1.1.
Configuration Mechanism SO-DIMMs ..........................................129
4.9.1.2.
DRAM Register Programming ......................................................129
4.9.2.
DRAM Address Translation and Decoding................................................130
4.9.3.
SDRAMT Register Programming ..............................................................131
4.9.4.
SDRAM Paging Policy...............................................................................131
Intel Dynamic Video Memory Technology (D.V.M.T.)................................................131
Display Cache Interface...............................................................................................132
4.11.1.
Supported DRAM Types for Display Cache Memory.................................132
4.11.2.
Memory Configurations..............................................................................133
4.11.3.
Address Translation...................................................................................133
4.11.4.
Display Cache Interface Timing.................................................................134
Internal Graphics Device..............................................................................................134
4.12.1.
3D/2D Instruction Processing....................................................................134
4.12.2.
3D Engine..................................................................................................135
4.12.3.
Buffers .......................................................................................................135
4.12.4.
Setup..........................................................................................................136
4.12.5.
Texturing....................................................................................................136
4.12.6.
2D Operation..............................................................................................138
4.12.7.
Fixed Blitter (BLT) and Stretch Blitter (STRBLT) Engines.........................139
4.12.7.1.
Fixed BLT Engine..........................................................................139
4.12.7.2.
Arithmetic Stretch BLT Engine......................................................139
4.12.8.
Hardware Motion Compensation ...............................................................140
4.12.9.
Hardware Cursor and Popup Support .......................................................140
4.12.10.
Overlay Engine ..........................................................................................140
4.12.11.
Display.......................................................................................................141
4.12.12.
Digital Video Out (DVO) Port.....................................................................142
4.12.12.1.
VCH interface................................................................................142
4.12.12.2.
DVO Port Data Format..................................................................143
4.12.12.3.
DVO Port I
C Functionality............................................................145
4.3.2.2.
4.4.
4.5.
4.6.
4.7.
4.8.
4.9.
4.10.
4.11.
4.12.
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