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| 型號： | 82815EM |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 17/163頁 |
| 文件大?。?/td> | 1049K |
| 代理商： | 82815EM |
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Intel
82815EM GMCH
R
Datasheet
17
The AGP interface supports 4x AGP signaling. AGP semantic (PIPE# or SBA[7:0]) cycles to SDRAM
are not snooped on the host bus. AGP FRAME# cycles to SDRAM are snooped on the host bus. The
GMCH2-M supports PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously. Either
the PIPE# or the SBA[7:0] mechanism must be selected during system initialization. High priority
accesses are supported. Only memory writes from the hub interface to AGP are allowed. No transactions
from AGP to the hub interface are allowed.
1.6.1.
Display Cache Interface
The Intel
815EM chipset integrates a Display Cache SDRAM controller for enhanced 3D performance.
The maximum memory support is 4 MB. The Display Cache Interface is multiplexed with the AGP
controller interface to provide options for both the value mobile segment and main stream performance
platforms configuration with the Intel
815EM chipset. When the AGP port is populated with an AGP
graphics device the integrated graphics is disabled and thus the display cache interface is not needed.
The Intel
815EM chipset GMCH2-M supports a Display Cache SDRAM controller with a 32-bit
133
MHz
SDRAM array. The DRAM type supported is industry standard Synchronous DRAM (SDRAM)
like that of the system memory. The local memory SDRAM controller interface is fully configurable
through a set of control registers. For more details on the registers, consult the
Extensions to the
Pentium
Pro Processor BIOS Writer’s Guide
Revision 3.6 and higher.
1.7.
Hub Interface
The hub interface is a private interconnect between the GMCH2-M and the ICH2-M.
1.8.
GMCH2-M Integrated Graphics (GFX) Support
The GMCH2-M includes a highly integrated 2D/3D graphics accelerator (GFX) and is PC99a compliant.
Its architecture consists of dedicated multi-media engines executing in parallel to deliver high
performance graphics and video capabilities which includes integrated 3D graphics engine, 2D graphics
engine, video engine, display pipeline, and motion compensation HW accelerator.
The 3D and 2D engines are managed by a 3D/2D pipeline preprocessor allowing a sustained flow of
graphics data to be rendered and displayed. The deeply pipelined 3D accelerator engine provides 3D
graphics quality and performance via per-pixel 3D rendering and parallel data paths which allow each
pipeline stage to simultaneously operate on different primitives or portions of the same primitive. The
GMCH2-M graphics accelerator engine supports perspective-correct texture mapping, trilinear and
anisotropic filtering, Mip-Mapping, Gouraud shading, alpha-blending, fogging and Z-buffering. A rich
set of 3D instructions permit these features to be independently enabled or disabled.
The GMCH2-M integrated graphics accelerator’s 2D capabilities include BLT and arithmetic STRBLT
engines, a hardware cursor, a popup window and an extensive set of 2D registers and instructions. The
high performance 64-bit BitBLT engine provides hardware acceleration for many common Windows
operations.
In addition to its 2D/3D capabilities, the GMCH2-M integrated graphics accelerator also supports full
MPEG-2 motion compensation for software-assisted DVD video playback, a VESA DDC2B compliant
display interface and a digital video out port to interface to the VCH for panel support.
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