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參數(shù)資料
| 型號(hào)： | 82803AAMRH-R |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 20/52頁 |
| 文件大小： | 322K |
| 代理商： | 82803AAMRH-R |
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82803AA MRH-R
R
Datasheet
20
3.6.
CCR—Clock Control Register
Address:
Default:
Access:
Size:
0Bh
0000h (bit ‘0’ is Read Only)
Read/Write
16 bits
Bit
Description
15:6
Reserved
5
DRCG B STOP#.
This bit is directly connected to the STOPB# pin on the MRH-R. This pin is then
connected to the STOP# pin on the channel B DRCG.
4
DRCG B PWRDN#.
This bit is directly connected to the PWRDNB# pin on the MRH-R. The PWRDNB#
pin is connected to the channel B external DRCG PWRDN# pin. Note that this pin defaults to ‘0’ so that
the DRCG is disabled at powerup.
3
DRCG A STOP#.
This bit is directly connected to the STOPA# pin on the MRH-R. This pin is then
connected to the STOP# pin on the channel A DRCG.
2
DRCG A PWRDN#.
This bit is directly connected to the PWRDNA# pin on the MRH-R. The PWRDNA#
pin is connected to the PWRDN# pin on the channel A external DRCG. Note that this pin defaults to ‘0’
so that the DRCG is disabled at powerup.
1
External Clock Generation.
When set to ‘1’, this bit indicates that external DRCGs will generate the
clocks for ‘stick’ channels A and B.
0
Expansion Skip Status Bit (ESS).
This bit contains a value indicating the phase relationship of the
CFM/CTM clocks.
3.7.
LMTR—Levelization Mode And Timing Register
Address:
0Eh
Default:
0000h
Access:
Bit 15 read only, bits 14:12 write-only,
bits 11:8, 7, 6:4, 3:0 are write-gated
Size:
16 bits
Bit
Description
15
Levelization Mode Status (LMS)—RO.
1 = MRH-R is in levelization mode. (i.e., via SLM command described below.)
0 = Normal operation for the MRH-R.
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