Signal Description
2-12
Intel
82801BA ICH2 Datasheet
2.19
Power and Ground
2.20
Pin Straps
2.20.1
Functional Straps
The following signals are used for static configuration. They are sampled at the rising edge of
PWROK to select configurations and then revert later to their normal usage. To invoke the
associated mode, the signal should be driven at least 4 PCI clocks prior to the time it is sampled.
Table 2-19. Power and Ground Signals
Name
Description
Vcc3_3
3.3V supply for Core well I/O buffers. This power may be shut off in S3, S5 or G3 states.
Vcc1_8
1.8V supply for Core well logic. This power may be shut off in S3, S5 or G3 states.
V5REF
Reference for 5V tolerance on Core well inputs. This power may be shut off in S3, S5 or
G3 states.
HUBREF
0.9V reference for the hub interface. This power may be shut off in S3, S5 or G3 states.
VccSus3_3
3.3V supply for Resume well I/O buffers. This power is not expected to be shut off unless
the system is unplugged.
VccSus1_8
1.8V supply for Resume well logic. This power is not expected to be shut off unless the
system is unplugged.
V5REF_SUS
Reference for 5V tolerance on Resume well inputs. This power is not expected to be shut
off unless the system is unplugged.
Note: V5REF_SUS only affects 5V tolerance for the USB OC[3:0]# pins and can be
connected to VccSUS3_3 if 5V tolerance on these signals is not required.
VccRTC
3.3V (can drop to 2.0V min. in G3 state) supply for the RTC well. This power is not
expected to be shut off unless the RTC battery is removed or completely drained.
Note: Implementations should not attempt to clear CMOS by using a jumper to pull
VccRTC low. Clearing CMOS in an ICH2-based platform can be done by using a jumper
on RTCRST# or GPI, or using SAFEMODE strap.
VBIAS
RTC well bias voltage. The DC reference voltage applied to this pin sets a current that is
mirrored throughout the oscillator and buffer circuitry. See
Section 2.20.3
.
V_CPU_IO
Powered by the same supply as the processor I/O voltage. This supply is used to drive the
processor interface outputs.
Vss
Grounds.
Table 2-20. Functional Strap Definitions
Signal
Usage
When
Sampled
Comment
AC_SDOUT
SAFE
MODE
Rising
Edge of
PWROK
The signal has a weak internal pull-down. If the signal is sampled
high, the ICH2 sets the processor speed strap pins for safe mode.
Refer to processor specification for speed strapping definition. The
status of this strap is readable via the SAFE_MODE bit (bit 2, D31:
F0, Offset D4h).
EE_DOUT
Reserved
System designers should include a placeholder for a pull-down
resistor on EE_DOUT but
do not populate the resistor
.
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