參數(shù)資料
型號(hào)： 82596SX
廠商： Intel Corp.
英文描述： HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR
中文描述： 高性能的32位局域網(wǎng)協(xié)處理器
文件頁(yè)數(shù)： 47/77頁(yè)
文件大?。?/td> 787K
代理商： 82596SX
82596DX/SX
where:
EOF
D This bit indicates that this TBD is the last one associated with the frame being
transmitted. It is set by the CPU before transmit.
SIZE (ACT COUNT)
D This 14-bit quantity specifies the number of bytes that hold information for the
current buffer. It is set by the CPU before transmission.
NEXT TBD ADDRESS
D In the 82586 and 32-bit Segmented modes, it is the offset of the next TBD on the
list. In the Linear mode this is the 32-bit address of the next TBD on the list. It is
meaningless if EOF
e
1.
D The starting address of the memory area that contains the data to be sent. In the
82586 mode, this is a 24-bit address (A31–A24 are considered to be zero). In the
32-bit Segmented and Linear modes this is a 32-bit address. This buffer can be
byte aligned for the 82596 B-step.
BUFFER ADDRESS
TDR
This operation activates Time Domain Reflectometry, which is a mechanism to detect open or short circuits on
the link and their distance from the diagnosing station. The TDR command has no parameters. The TDR
transmit sequence was changed, compared to the 82586, to form a regular transmission. The TDR command
is designed to be used statically. Make sure that both the CU and RU are idle before attempting a TDR
command. The TDR bit stream is as follows.
D Preamble
D Source address
D Another Source address (the TDR frame is transmitted back to the sending station,
so DEST ADR
e
SRC ADR).
D Data field containing 7Eh patterns.
D Jam Pattern, which is the inverse CRC of the transmitted frame.
Maximum length of the TDR frame is 2048 bits. If the 82596 senses collision while transmitting the TDR frame
it transmits the jam pattern and stops the transmission. The 82596 then triggers an internal timer (STC); the
timer is reset at the beginning of transmission and reset if CRS is returned. The timer measures the time
elapsed from the start of transmission until an echo is returned. The echo is indicated by Collision Detect going
active or a drop in the Carrier Sense signal. The following table lists the possible cases that the 82596 is able
to analyze.
Conditions of TDR as Interpreted by the 82596
Transceiver Type
Ethernet
Non Ethernet
Condition
Carrier Sense was inactive for 2048-bit-time
periods
Short or Open on the
Transceiver Cable
NA
Carrier Sense signal dropped
Short on the Ethernet cable
NA
Collision Detect went active
Open on the Ethernet cable
Open on the Serial Link
The Carrier Sense Signal did not drop or the
Collision Detect did not go active within
2048-bit time period
No Problem
No Problem
An Ethernet transceiver is defined as one that returns transmitted data on the receive pair and activates the
Carrier Sense Signal while transmitting. A Non-Ethernet Transceiver is defined as one that does not do so.
47
相關(guān)PDF資料
PDF描述
82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR
8261SHAKE22 Alternate Action and Momentary Pushbutton Switches
8261SHAKE223 Alternate Action and Momentary Pushbutton Switches
8261SHAPE22 Alternate Action and Momentary Pushbutton Switches
8261SHAPE223 Alternate Action and Momentary Pushbutton Switches
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