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參數(shù)資料
| 型號： | 82596CA |
| 廠商： | Intel Corp. |
| 英文描述： | HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR |
| 中文描述： | 高性能的32位局域網(wǎng)協(xié)處理器 |
| 文件頁數(shù)： | 36/77頁 |
| 文件大?。?/td> | 787K |
| 代理商： | 82596CA |
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82596DX/SX
where:
LINK POINTER
D In the 82586 or 32-bit Segmented modes this is a 16-bit offset to the next Command
Block. In the Linear mode this is the 32-bit address of the next Command Block.
EL
D If set, this bit indicates that this command block is the last on the CBL.
S
D If set to one, suspend the CU upon completion of this CB.
I
D If set to one, the 82596 will generate an interrupt after execution of the command is
complete. If I is not set to one, the CX bit will not be set.
CMD (bits 16–18) D The NOP command. Value: 0h.
Bits 19–28
D Reserved (zero in the 32-bit Segmented and Linear modes).
C
D This bit indicates the execution status of the command. The CPU initially resets it to zero
when the Command Block is placed on the CBL. Following a command Completion, the
82596 will set it to one.
B
D This bit indicates that the 82596 is currently executing the NOP command. It is initially
reset to zero by the CPU. The 82596 sets it to one when execution begins and to zero
when execution is completed. This bit is also set when the 82596 prefetches the com-
mand.
NOTE:
The C and B bits are modified in one operation.
OK
D Indicates that the command was executed without error. If set to one no error occurred
(command executed OK). If zero an error occur.
INDIVIDUAL ADDRESS SETUP
This command is used to load the 82596 with the Individual Address. This address is used by the 82596 for
inserting the Source Address during transmission and recognizing the Destination Address during reception.
After RESET, and prior to Individual Address Setup Command execution, the 82596 assumes the Broadcast
Address is the Individual Address in all aspects, i.e.:
#
This will be the Individual Address Match reference.
#
This will be the Source Address of a transmitted frame (for AL-LOC
e
0 mode only).
The format of the Individual Address Setup command is shown in Figure 22.
IA SetupD82586 and 32-Bit Segmented Modes
16
ODD WORD
31
15
0
EVEN WORD
EL S
I
X
X
X
X
X
X
X
X
X
X
0
0
1
C
B OK A
0
0
0
0
0
0
0
0
0
0
0
0 0
INDIVIDUAL ADDRESS
1st byte A15
A0
LINK OFFSET
4
6th byte
5th byte
4th byte
3rd byte
8
IA SetupDLinear Mode
16
15
31
ODD WORD
0
EVEN WORD
EL S
I
0
0
0
0
0
0
0
0
0
0
0
0
1
C
B OK A
0
0
0
0
0
0
0
0
0
0
0
0 0
A31
A0
LINK ADDRESS
4
4th byte
3rd byte
INDIVIDUAL ADDRESS
1st byte
8
6th byte
5th byte
C
Figure 22
where:
LINK ADDRESS,
EL, B, C, I, S
D As per standard Command Block (see the NOP command for details)
A
D Indicates that the command was abnormally terminated due to CU Abort control
command. If one, then the command was aborted, and if necessary it should be
repeated. If this bit is zero, the command was not aborted.
36
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|---|---|
| 82596DX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR |
| 82596SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR |
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