參數(shù)資料
型號: 82555
廠商: INTEL CORP
元件分類: 網(wǎng)絡(luò)接口
英文描述: 10/100 Mbps LAN physical layer interface
中文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP100
封裝: PLASTIC, MQFP-100
文件頁數(shù): 46/58頁
文件大?。?/td> 863K
代理商: 82555
82555 — Networking Silicon
42
Datasheet
The TOUT pin is controlled by different sources according to the active test instruction. The TOUT
signal is activated by the falling edge of TCK. The TAP must be reset during power-up. Otherwise,
the 82555 can wake-up during high-Z mode or NAND Test, which can be harmful to the board.
The TAP should be reset only with a hardware reset input pin and not with software reset. The
TOUT control logic selects the TISR output in all tests, except burn-in test modes.
Table 6. Test Instruction Coding
Number
Code
Test Instruction
Select Input to TOUT
1
00000
Idle
TISR D4out
2
00001
Reserved
TISR D4out
3
00010
High-Z
High-Z
4
00011
NAND Test
TISR D4out
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