參數(shù)資料
型號: 82375EB
廠商: INTEL CORP
元件分類: 總線控制器
英文描述: PCI-EISA BRIDGE (PCEB)
中文描述: EISA BUS CONTROLLER
文件頁數(shù): 85/131頁
文件大小: 1337K
代理商: 82375EB
82375EB/SB
5.4 PCI Bus Arbitration
The PCEB contains a PCI Bus arbiter that supports six PCI Bus mastersThe Host/PCI Bridge, PCEB, and four
other masters. The PCEB’s REQ
Y
/GNT
Y
signals are internal. An external arbiter is not supported. Note that,
for proper arbiter operation, CPUREQ
Y
must be sampled high by the PCEB when PCIRST
Y
makes a low-to-
high transition. The internal arbiter contains several features that contribute to system efficiency:
#
Use of the internal RESUME
Y
signal to re-enable a backed-off initiator in order to minimize PCI Bus
thrashing when the PCEB generates a retry.
#
A programmable timer to re-enable retried initiators after a number of PCICLK’s.
#
A programmable PCI Bus lock or PCI resource lock function.
#
The CPU Host/PCI can be optionally parked on the PCI Bus.
In addition, the PCEB has three PCI sideband signals (FLUSHREQ
Y
, MEMREQ
Y
, and MEMACK
Y
) that are
used to control system buffer coherency and control operations for the Guaranteed Access Time (GAT) mode.
5.4.1 PCI ARBITER CONFIGURATION
The PCI arbitration priority scheme is programmable through the configuration registers. The arbiter consists
of four banks that can be configured so that the six masters to be arranged in a purely rotating priority scheme,
one of 24 fixed priority schemes, or a hybrid combination (Figure 21).
85
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