參數(shù)資料
型號(hào)： 82375EB
廠商： INTEL CORP
元件分類： 總線控制器
英文描述： PCI-EISA BRIDGE (PCEB)
中文描述： EISA BUS CONTROLLER
文件頁數(shù)： 45/131頁
文件大?。?/td> 1337K
代理商： 82375EB
82375EB/SB
Bit
Description
7:4
Reserved
3
Region 4 Attribute (REG-4):
EISA accesses to this PCI memory region are buffered when this bit is 1
and non-buffered when this bit is 0. If the Line Buffers are disabled via the PCICON Register (bit 6),
buffering is disabled, regardless of the value of this bit.
2
Region 3 Attribute (REG-3):
EISA accesses to this PCI memory region are buffered when this bit is 1
and non-buffered when this bit is 0. If the Line Buffers are disabled via the PCICON Register (bit 6),
buffering is disabled, regardless of the value of this bit.
1
Region 2 Attribute (REG-2):
EISA accesses to this PCI memory region are buffered when this bit is 1
and non-buffered when this bit is 0. If the Line Buffers are disabled via the PCICON Register (bit 6),
buffering is disabled, regardless of the value of this bit.
0
Region 1 Attribute (REG-1):
EISA accesses to this PCI memory region are buffered when this bit is 1
and non-buffered when this bit is 0. If the Line Buffers are disabled via the PCICON Register (bit 6),
buffering is disabled, regardless of the value of this bit.
3.1.23 MEMREGN
[
4:1
]
DEISA-TO-PCI MEMORY REGION ADDRESS REGISTERS
Address Offset:
60-63h (Memory Region 1)
64-67h (Memory Region 2)
68-6Bh (Memory Region 3)
6C-6Fh (Memory Region 4)
0000FFFFh
Read/Write
32 bits
Default Value:
Attribute:
Size:
These 32-bit registers provide four windows for EISA-to-PCI memory accesses. Each window defines a posi-
tively decoded programmable address region for mapping EISA memory space to the corresponding PCI
memory space. This base and limit address fields define the size and location of the region within the 4 GByte
PCI memory space. The base and limit addresses can be aligned on any 64 KByte boundary and each region
can be sized in 64 KByte increments, up to the theoretical maximum size of 4 GByte. The default values of this
register ensure that the regions are initially disabled.
A region is selected based on the following formula: Base Address
s
address
s
Limit Address.
Bit
Description
31:16
Memory Region Limit Address:
For EISA-to-PCI accesses, bits
[
31:16
]
correspond to address
lines LA
[
31:16
]
on the EISA Bus and AD
[
31:16
]
on the PCI Bus. This field determines the limit
address of the memory region within the 4 GByte PCI memory space.
Memory Region Base Address:
For EISA-to-PCI accesses, bits
[
15:0
]
correspond to address lines
LA
[
31:16
]
on the EISA Bus and AD
[
31:16
]
on the PCI Bus. This field determines the starting
address of the memory region within the 4 GByte PCI memory space.
15:0
45
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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