參數(shù)資料
型號(hào)： 7P032FLF1200C20
英文描述： Peripheral Miscellaneous
中文描述： 周邊雜項(xiàng)
文件頁(yè)數(shù)： 12/17頁(yè)
文件大小： 202K
代理商： 7P032FLF1200C20
November 2000 Rev. 3 - ECO #13392
4
PCMCIA Flash Memory Card
FLF10 Series
PC Card Products
Symbol
Type
Name and Function
A0 - A25
INPUT
ADDRESS INPUTS: A0 through A25 enable direct addressing of up
to 64MB of memory on the card. Signal A0 is not used in word access
mode. A25 is the most significant bit
DQ0 - DQ15
INPUT/OUTPUT
DATA INPUT/OUTPUT: DQ0 THROUGH DQ15 constitute the
bi-directional databus. DQ15 is the MSB.
CE1#, CE2#
INPUT
CARD ENABLE 1 AND 2: CE1# enables even byte accesses, CE2#
enables odd byte accesses. Multiplexing A0, CE1# and CE2# allows 8-
bit hosts to access all data on DQ0 - DQ7 (see truth table).
OE#
INPUT
OUTPUT ENABLE: Active low signal gating read data from the
memory card.
WE#
INPUT
WRITE ENABLE: Active low signal gating write data to the memory
card.
RDY/BSY #
OUTPUT
READY/BUSY OUTPUT: Indicates status of internally timed erase
or program algorithms. A high output indicates that the card is ready to
accept accesses. A low output indicates that one or more devices in the
memory card are busy with internally timed erase or write activities.
CD1#, CD2#
OUTPUT
CARD DETECT 1 and 2: Provide card insertion detection. These
signals are internally connected to ground on the card. The host shall
monitor these signals to detect card insertion. Pulled up on host side.
WP
OUTPUT
WRITE PROTECT: Write protect reflects the status of the Write
Protect switch on the memory card. WP set to high = write protected,
providing internal hardware write lockout to the Flash array.
If card does not include optional write protect switch, this signal will be
pulled low internally indicating write protect = "off".
VPP1, VPP2
N.C.
PROGRAMMING VOLTAGES: Not connected
VCC
CARD POWER SUPPLY: Universal 3V to 5V Supply
GND
CARD GROUND
REG#
INPUT
ATTRIBUTE MEMORY SELECT: Active low signal, enables
access to attribute memory space, occupied by the Card Information
Structure (CIS) and Card Registers.
RST
INPUT
RESET: Active high signal for placing card in Power-on default state.
Reset can be used as a Power-Down control for the memory array.
WAIT #
OUTPUT
WAIT: This signal is pulled high internally for compatibility. No wait
states are generated.
BVD1, BVD2
OUTPUT
BATTERY VOLTAGE DETECT: These signals are pulled high to
maintain SRAM card compatibility.
VS1, VS2
OUTPUT
VOLTAGE SENSE: Notifies the host socket of the card's VCC
requirements. VS1 grounded and VS2 is open to indicate a 3/5V card.
RFU
RESERVED FOR FUTURE USE
N.C.
NO INTERNAL CONNECTION TO CARD: pin may be driven
or left floating.
READ function
Common Memory
Attribute Memory
Function Mode
/CE2
/CE1
A0
/OE
/WE
/REG
D15-D8
D7-D0
/REG
D15-D8
D7-D0
Standby Mode
H
X
High-Z
X
High-Z
Byte Access (8 bits)
H
L
H
High-Z
Even-Byte
L
High-Z
Even-Byte
HL
H
L
H
High-Z
Odd-Byte
L
High-Z
Not Valid
Word Access (16 bits)
L
X
L
H
HOdd-Byte Even-Byte
LNot Valid
Even-Byte
Odd-Byte Only Access
L
H
X
L
H
Odd-Byte
High-Z
L
Not Valid
High-Z
WRITE function
Standby Mode
H
X
XX
X
XX
X
Byte Access (8 bits)
HL
LHL
HX
Even-Byte
LX
Even-Byte
HL
H
L
HX
Odd-Byte
LX
X
Word Access (16 bits)
L
X
H
L
HOdd-Byte Even-Byte
LX
Even-Byte
Odd-Byte Only Access
L
H
X
H
L
HOdd-Byte
X
LX
X
Card Signal Description
Functional Truth Table
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