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IDT General Purpose I/O Controller
Theory of Operation
79RC32438 User Reference Manual
12 - 2
November 4, 2002
Notes
Theory of Operation
After reset, all GPIO pins default to the GPIO input function. When a GPIO pin is configured for use as a
GPIO pin, the alternate function associated with that pin is held in an inactive state by internal logic. Care
should be exercised when configuring GPIO pins as outputs because an incorrect configuration (for
example, mistakenly configuring an input pin as an output pin) could cause damage to external components
as well as to the RC32438 device itself.
Each GPIO pin is controlled by its corresponding bit in each GPIO register. For example, GPIO bit [0] is
controlled by GPIOFUNC[0], GPIOCFG[0], GPIOD[0], GPIOILEVEL[0], GPIOISTAT[0], and
GPIONMIEN[0]. In another example, GPIO bit [2] is controlled by GPIOFUNC[2], GPIOCFG[2], GPIOD[2],
GPIOILEVEL[2], GPIOISTAT[2], and GPIONMIEN[2].
All GPIO pins except GPIO[24] and GPIO[30:26] have LVTTL I/O buffers. GPIO pins 24 and 26 through
30 have PCI I/O buffers which allow these pins to be used for PCI interrupts.
GPIO Pin Configured As Input
When configured as an input in the GPIO configuration register (GPIOCFG) and as a GPIO function in
the GPIO function register (GPIOFUNC), the GPIO pin value will be sampled and registered in the GPIO
data register (GPIOD) each master clock cycle (after double registering to prevent metastability). The value
of the input pin can be determined at any time by reading GPIOD.
16
DMADONEN0
External DMA channel 0 done (see Chapter 9)
Input
17
DMADONEN1
External DMA channel 1 done (see Chapter 9)
Input
18
DMAFINN0
External DMA channel 0 finished (see Chapter 9)
Output
19
DMAFINN1
External DMA channel 1 finished (see Chapter 9)
Output
20
MADDR[22]
Memory and peripheral bus address (see Chapter 6)
Output
21
MADDR[23]
Memory and peripheral bus address (see Chapter 6)
Output
22
MADDR[24]
Memory and peripheral bus address (see Chapter 6)
Output
23
MADDR[25]
Memory and peripheral bus address (see Chapter 6)
Output
24
PCIREQN[4]
PCI Request 4 (see Chapter 10)
Input
25
AFSPARE1
reserved
Input
26
PCIGNTN[4]
PCI Grant 4 (see Chapter 10)
Output
27
PCIREQN[5]
PCI Request 5 (see Chapter 10)
Input
28
PCIGNTN[5]
PCI Grant 5 (see Chapter 10)
Output
29
IPBMTRIGINP
IPBus monitor trigger input (see Chapter 19)
Input
30
PCIMUINTN
1
PCI messaging unit interrupt output (see Chapter 10)
Output
31
Reserved
1.
When acting as the alternate function PCIMUINTN, this pin is tri-stated when it is not asserted (i.e., it acts as an open collector
output when configured as an alternate function).
GPIO
Pin
Alternate
Function
Pin Name
Alternate Function Description
Alternate
Function
Pin Type
Table 12.1 General Purpose I/O Pin Alternate Function (Part 2 of 2)