參數(shù)資料
型號(hào): 79RC32T355180DHI
廠商: Integrated Device Technology, Inc.
英文描述: Communications Processor
中文描述: 通信處理器
文件頁(yè)數(shù): 15/47頁(yè)
文件大?。?/td> 987K
代理商: 79RC32T355180DHI
15 of 47
May 25, 2004
IDT 79RC32355
Clock Parameters
(Ta = 0
°
C to +70
°
C Commercial, Ta = -40
°
C to +85
°
C Industrial, Vcc I/O = +3.3V
±
5%,V
cc
Core and V
cc
P = +2.5V
±
5%)
Figure 4 Clock Parameters Waveform
Parameter
Symbol
Reference
Edge
133MHz
150MHz
180MHz
Units
Timing
Diagram
Reference
Min
Max
Min
Max
Min
Max
Internal CPU pipeline clock
1
Frequency
none
100
133
100
150
100
180
MHz
Figure 4
CLKP
2,3,4
Frequency
none
25
67
25
75
25
90
MHz
Tperiod1
15
40
13.3
40
11.1
40
ns
Thigh1
6
5.4
5.4
ns
Tlow1
6
5.4
5.4
ns
Trise1
3
2.5
2.5
ns
Tfall1
3
2.5
2.5
ns
Tjitter
±250
±200
±200
ps
1
The CPU pipeline clock speed is selected during cold reset by the boot configuration vector (see Table 2).
2
Ethernet clock (MIIRXCLKP and MIITXCLKP) frequency must be equal to or less than 1/2 CLKP frequency.
3
USB clock (USBCLKP) frequency must be less than CLKP frequency.
4
ATM Utopia clock (RXCLKP and TXCLKP) frequency must be equal to or less than 1/2 CLKP frequency.
Table 3 Clock Parameters
Tlow1
Thigh1
Tperiod1
CLKP
Trise1
Tfall1
Tjitter
Tjitter
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