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June 20, 2000
2000 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
DSC 4510
Block Diagram
The IDT logo is a registered trademark and ORION, RC4650, RC4640, RV4640, RC4600, RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
System Control
Coprocessor (CPO)
2kB D-Cache, 2-set,
lockable, write-back/write-through
Clock
Generation
Unit
E
TLB
MMU
w/
RC32364 Bus Interface Unit
8kB I-Cache,
2-set,
lockable
RISCore32300 Internal Bus Interface
RISCore4000 Compatible
RISCore32300
TM
Extended MIPS 32
Integer CPU Core
Features
N
High-performance embedded RISController
TM
microprocessor, based on IDT RISCore32300
TM
32-bit CPU
core
–
Based on MIPS 32 RISC architecture with enhancements
–
Scalar 5-stage pipeline minimizes branch and load delays
–
66 Million multiply accumulate (MAC) Mul-Add/second
@ 133MHz
–
100 and 133 frequencies
N
MIPS 32 (ISA) instruction set architecture
–
MIPS IV compatible conditional move instructions
–
MIPS IV superset PREF (prefetch) instruction
–
Fast multiplier with atomic multiply-add, multiply-sub
–
Count leading zeros/ones instructions
N
Large, efficient on-chip caches
–
Separate 8kB Instruction cache and 2kB Data cache
–
2-way set associative
–
Write-back and write-through support on a per page basis
–
Optional cache locking with “per line” resolution, to facilitate
deterministic response
–
Simultaneous instruction and data fetch in each clock cycle,
sustained rate, achieves over 1 GB/sec bandwidth
N
Flexible RC4000 compatible MMU with 32-page TLB on-chip
–
Variable page size
–
Variable number of locked entries
–
No performance penalty for address translation
N
Flexible bus interface allows simple, low-cost designs
–
Bus interface runs at a fraction of pipeline rate
–
Programmable port-width interface (8-,16-, 32-bit memory and
I/O regions)
–
Programmable bus turnaround times (BTA)
–
Supports single data or burst transactions
N
Improved real-time support
–
Fast interrupt decode
N
Low-power operation
–
Active power management: powers down inactive units
–
Typical power 700mW @ 133MHz
–
Stand-by mode <300mW
N
Enhanced JTAG interface, for low-cost in-circuit emulation
(ICE)
N
MIPS architecture ensures applications software
compatibility throughout the RISController series of
embedded processors
N
Industrial temperature range support
N
3.3V operation (core and I/O)
79RC32364
RISController
TM
Embedded 32-bit
Microprocessor, based on
RISCore32300