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參數(shù)資料
| 型號： | 79RC32364 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | RISController Embedded 32-bit Microprocessor, based on RISCore32300 |
| 中文描述： | RISController嵌入式32位的基礎(chǔ)上RISCore32300微處理器， |
| 文件頁數(shù)： | 12/21頁 |
| 文件大?。?/td> | 370K |
| 代理商： | 79RC32364 |
12 of 21
June 20, 2000
79RC32364
Absolute Maximum Ratings
Note:
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
*Notice: The information in this document is subject to change without notice
Recommended Operation Temperature and Supply Voltag
AC Electrical Characteristics — Commercial/Industrial Temperature
Ranges—RC32364
V
CC
Core & V
CC
I/O = 3.3V
±
5%; T
Case
= 0
°
C to +85
°
C Commercial, T
Case
= -40
°
C to +85
°
C Industrial
Clock Parameters—RC32364
Note:
Operation of the RC32364 is only guaranteed with the Phase Lock Loop enabled
Symbol
Rating
RC32364
3.3V
±
5%
RC32364
3.3V
±
5%
Unit
Commercial
Industrial
–0.5
1
to 4.0
V
TERM
T
C
T
BIAS
T
STG
I
IN
I
OUT
Terminal Voltage with respect to GND –0.
5
1
to 4.0
1.
V
IN
minimum = –2.0V for pulse width less than 15ns. V
IN
should not exceed V
CC
+0.5 Volts.
2.
When V
IN
< 0V or V
IN
> V
CC
3.
Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.
V
Operating Temperature(case)
0 to +85
-40 to +85
°
C
°
C
°
C
mA
Case Temperature Under Bias
–55 to +125
–55 to +125
Storage Temperature
–55 to +125
20
2
50
3
–55 to +125
20
2
50
3
DC Input Current
DC Output Current
mA
Grade
Temperature
Gnd
RC32364
V
CC Core & Vcc I/O
3.3V
±
5%
3.3V
±
5%
Commercial
0
°
C to +85
°
C (Case)
-40
°
C + 85
°
C (Case)
0V
Industrial
0V
Parameter
Symbol
Test
Conditions
RC32364 100MHz
RC32364 133MHz
Units
Min
Max
Min
Max
Pipeline clock frequency
PClk
80
100
80
133
MHz
MasterClock HIGH
t
MCHIGH
t
MCLOW
Transition
≤
2ns
Transition
≤
2ns
—
6
—
5
—
ns
MasterClock LOW
6
—
5
—
ns
MasterClock Frequency
—
t
MCP
t
JitterIn1
t
MCRise
t
MCFall
t
TCK
t
TCKLOW,
t
TCKHIGH
t
TCKFall,
t
TCKRise
10
50
10
67
MHz
MasterClock Period
Clock Jitter for MasterClock
1
MasterClock Rise Time
2
MasterClock Fall Time
2
—
20
100
±
250
3
15
100
±
250
3
ns
1.
Guaranteed by design
2.
Rise and Fall times are measured between 10% and 90%.
—
—
—
ps
—
—
—
ns
—
—
3
—
3
ns
JTAG Clock Period
—
100
—
100
—
ns
JTAG Clock High and Low Time
—
40
—
40
—
ns
JTAG Clock Fall and Rise Time
—
—
3
—
3
ns
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