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參數(shù)資料
| 型號： | 78Q2120 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10/100BASE-TX Ethernet Transceiver |
| 中文描述： | 10/100BASE-TX以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 16/33頁 |
| 文件大小： | 200K |
| 代理商： | 78Q2120 |
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78Q2120
10/100BASE-TX
Ethernet Transceiver
MR16 - VENDOR SPECIFIC REGISTER
(continued)
16
BIT
SYMBOL
TYPE
DESCRIPTION
16.1
PCSBP
R,W,0
PCS BYPASS: When set, the 100BASE-TX PCS is bypassed, as
are the scrambler and descrambler functions. Scrambled 5-bit code
groups for transmission are applied to the TX_ER, TXD[3:0] pins
and received on the RX_ER, RXD[3:0] pins. The RX_DV and
TX_EN signals are not valid in this mode. PCSBP mode is only valid
when 100BASE-TX is enabled.
16.0
RXCC
R,W,0
RECEIVE CLOCK CONTROL: When set, the RX_CLK signal will
be held in logic low (only in 100BASE-TX mode) when there is no
data being received (to save power). The RX_CLK signal will restart
1 clock cycle before the assertion of RX_DV and be shut off 64 clock
cycles after RX_DV goes low. RXCC is disabled when loopback
mode is enabled (MR0.14 is high). This bit should be kept at logic
zero when the chip is in PCS Bypass mode.
MR17 - INTERRUPT CONTROL/STATUS REGISTER
The Interrupt Control/Status Register provides the means for controlling and observing the events which trigger
an interrupt on the INTR pin. This register can also be used in a polling mode via the MII serial interface as a
means to observe key events within the PHY via one register address. These bits are cleared after the register is
read. Bits 8-15 of this register, when set to logic one, enable their corresponding bit in the lower byte to signal an
interrupt on the INTR pin. The level of this interrupt can be set via MR16.14.
17.15
17.14
17.13
17.12
17.11
17.10
17.9
17.8
17.7
JABBER IE
RXER IE
PRX IE
PFD IE
LP-AC K IE
LS-CHG IE
RFAULT IE
ANEG-COMP IE
JABBER INT
R, W, 0
R, W, 0
R, W, 0
R, W, 0
R, W, 0
R, W, 0
R, W, 0
R, W, 0
RC, 0
JABBER INTERRUPT ENABLE BIT
RECEIVE ERROR INTERRUPT ENABLE BIT
PAGE RECEIVED INTERRUPT ENABLE BIT
PARALLEL DETECT FAULT INTERRUPT ENABLE BIT
LINK PARTNER ACKNOWLEDGE INTERRUPT ENABLE BIT
LINK STATUS CHANGE INTERRUPT ENABLE BIT
REMOTE FAULT INTERRUPT ENABLE BIT
AUTO-NEGOTIATION COMPLETE INTERRUPT ENABLE BIT
JABBER INTERRUPT: This bit is set when a jabber event is indicated
by the 10BASE-T circuitry.
RECEIVE ERROR INTERRUPT: This bit is set when the RX_ER
signal transitions high.
PAGE RECEIVE INTERRUPT: This bit is set when a new page has
been received from the link partner during auto-negotiation.
PARALLEL DETECT FAULT INTERRUPT: This bit is set by the auto-
negotiation logic when a parallel detect fault condition is indicated.
LINK PARTNER ACKNOWLEDGE INTERRUPT: This bit is set by the auto-
negotiation logic when FLP bursts are received with the acknowledge bit set.
LINK STATUS CHANGE INTERRUPT: This bit is set when the link
transitions from an OK status to a fail status or vice versa.
REMOTE FAULT INTERRUPT: This bit is set when a remote fault
condition has been indicated by the link partner.
AUTO-NEGOTIATION COMPLETE INTERRUPT: This bit is set by the
auto-negotiation logic upon successful completion of auto-negotiation.
17.6
RXER INT
RC, 0
17.5
PRX INT
RC, 0
17.4
PDF INT
RC, 0
17.3
LP-ACK INT
RC, 0
17.2
LS-CHG INT
RC, 0
17.1
RFAULT INT
RC, 0
17.0
ANEG-COMP INT
RC, 0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 78Q2120-64 | 10/100BASE-TX Ethernet Transceiver |
| 78Q2120-64CG | 10/100BASE-TX Ethernet Transceiver |
| 78Q2120-64CGT | 10/100BASE-TX Ethernet Transceiver |
| 78Q2120-64T | 10/100BASE-TX Ethernet Transceiver |
| 78Q2120-CGT | 10/100BASE-TX Ethernet Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 78Q2120-64 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100BASE-TX Ethernet Transceiver |
| 78Q2120-64CG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100BASE-TX Ethernet Transceiver |
| 78Q2120-64CGT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100BASE-TX Ethernet Transceiver |
| 78Q2120-64T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100BASE-TX Ethernet Transceiver |
| 78Q2120C | 制造商:TDK 制造商全稱:TDK Electronics 功能描述:10/100BASE - TX Transceiver |
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