參數(shù)資料
型號(hào)： 78Q2120-64
廠商： Electronic Theatre Controls, Inc.
英文描述： 10/100BASE-TX Ethernet Transceiver
中文描述： 10/100BASE-TX以太網(wǎng)收發(fā)器
文件頁(yè)數(shù)： 12/33頁(yè)
文件大小： 200K
代理商： 78Q2120-64
78Q2120
10/100BASE-TX
Ethernet Transceiver
MR0 - CONTROL REGISTER
(continued)
12
BIT
SYMBOL
TYPE
DESCRIPTION
0.8
DUPLEX
R, W, (1)
DUPLEX MODE: This bit determines whether the 78Q2120
supports full duplex or half duplex. A logic one indicates full duplex
operation and a logic zero indicates half duplex. When auto-
negotiation is enabled, this bit will have no effect on the 78Q2120.
At reset, this bit reflects the highest operating mode allowed by the
TECH [2:0] pins. The MII can write to this bit, but the bit will change
value only if the new value is allowed by the TECH pins.
0.7
COLT
R, W, 0
COLLISION TEST: When this bit is set to one, the 78Q2120 will
assert the COL signal in response to the assertion of TX_EN signal.
Collision test is disabled in PCS bypass mode. Collision test is
enabled regardless of the duplex mode of operation.
0.6:0
RSVD
R, 0
RESERVED
MR1 - STATUS REGISTER
Bits 1.15 through 1.11 reflect the ability of the 78Q2120 as configured by the TECH[2:0] pins They do not reflect any
ability changes made via the MII management interface to bits 0.13 (SPEEDSL), 0.12 (ANEGEN) and 0.8 (DUPLEX).
BIT
SYMBOL
TYPE
DESCRIPTION
1.15
100T4
R, 0
100BASE-T4 ABILITY: This bit is permanently held at logic zero to
indicate that the 78Q2120 is not capable of 100BASE-T4.
1.14
100X_F
R, (1)
100BASE-TX FULL DUPLEX ABILITY: (0 = not able, 1 = able)
1.13
100X_H
R, (1)
100BASE-TX HALF DUPLEX ABILITY: (0 = not able, 1 = able)
1.12
1.11
10T_F
10T_H
R, (1)
R, (1)
10BASE-T FULL DUPLEX ABILITY: (0 = not able, 1 = able)
10BASE-T HALF DUPLEX ABILITY: (0 = not able, 1 = able)
1.10:6
RSVD
R, 0
RESERVED
1.5
ANEGC
R, 0
AUTO-NEGOTIATION COMPLETE: A logic one indicates a) that
the auto-negotiation process has completed, b) that the contents of
registers MR4, 5, and 6 are valid, and c) that a highest common
denominator rate and mode have been found.
1.4
RFAULT
R, 0, RC
REMOTE FAULT: A logic one indicates that a remote fault condition has
been detected. It remains set until it is cleared. This bit can only be
cleared by reading this register (MR1) via the management interface.
1.3
ANEGA
R, (1)
AUTO-NEGOTIATION ABILITY: This bit, when set, indicates the
ability to perform auto-negotiation. The value of this bit is
determined by the ANEGA pin.
1.2
LINK
R, 0
LINK STATUS: A logic one indicates that a valid link has been
established. If the link status should transition from an OK status to
a NOT-OK status, this bit will become cleared and remain cleared
until it is read.
1.1
JAB
R, 0, RC
JABBER DETECT: In 10Base-T mode, this bit is set during a jabber
event. After a jabber event it remains set until cleared by a read operation.
1.0
EXTD
R, 1
EXTENDED CAPABILITY: This bit is permanently set to logic one
to indicate that the 78Q2120 provides an extended register set
(MR2 and beyond).
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