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參數(shù)資料
| 型號： | 78Q2120-64 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10/100BASE-TX Ethernet Transceiver |
| 中文描述： | 10/100BASE-TX以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 11/33頁 |
| 文件大小： | 200K |
| 代理商： | 78Q2120-64 |
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78Q2120
10/100BASE-TX
Ethernet Transceiver
MR0 - CONTROL REGISTER
11
BIT
SYMBOL
TYPE
DESCRIPTION
0.15
RESET
R, W, 0, SC
RESET: Setting this bit to logic one resets the entire 78Q2120. This
bit is self clearing.
0.14
LOOPBK
R, W, 0
LOOPBACK: When this bit is set, no transmission of data on the
network medium occurs and any receive data on the network
medium is ignored. By default, the loopback signal path will
encompass as much of the 78Q2120 circuitry as possible.
0.13
SPEEDSL
R, W, (1)
SPEED SELECTION: This bit determines the speed of operation of
the 78Q2120. A logic one indicates 100BASE-TX operation and a
logic zero indicates 10BASE-T. When auto-negotiation is enabled,
this bit will have no effect on the 78Q2120. At reset, this bit reflects
the highest operating speed allowed by the TECH [2:0] pins. The
MII can write to this bit, but the bit will change value only if the new
value is allowed by the TECH [2:0] pins.
0.12
ANEGEN
R, W, (1)
AUTO-NEGOTIATION ENABLE: The auto-negotiation process is
enabled by setting this bit to a logic one. This bit can only be set to
logic one if the ANEGA
pin is a logic one and will default to a logic
one upon reset in this case. If this bit is cleared to logic zero,
manual speed and duplex mode selection is accomplished through
bits 0.8 (DUPLEX) and 0.13 (SPEEDSL) of the configuration
register or the TECH[2:0] pins according to the table shown in the
section describing the TECH[2:0] pins. If the ANEGA
pin is brought
from zero to one and reset is not asserted, this bit will remain at
zero until a one is written.
0.11
PWRDN
R, W, 0
POWER-DOWN: The 78Q2120 may be placed in a low power
consumption state by setting this bit to logic one. While in
power-down state, the 78Q2120 still responds to management
transactions. The power-down state can also be achieved by setting
PWRDN pin high.
0.10
ISO
R, W, (0)
ISOLATE: When set, the 78Q2120 will present a high impedance
on its MII output pins. This allows for multiple PHY to be attached to
the same MII interface. When the 78Q2120 is isolated, it stills
responds to management transactions. The default value of this bit
depends on the ISODEF pin. When ISODEF pin is tied high the ISO
bit defaults to high. When ISODEF pin is tied low, the ISO bit
defaults to low. The same high impedance state can be achieved
through the ISO pin.
0.9
RANEG
R, W, 0, SC
RESTART AUTO-NEGOTIATION: Normally, the auto-negotiation
process is started at power-up. The process can be restarted by
setting this bit to logic one. This bit is self clearing.
相關PDF資料 |
PDF描述 |
|---|---|
| 78Q2120-64CG | 10/100BASE-TX Ethernet Transceiver |
| 78Q2120-64CGT | 10/100BASE-TX Ethernet Transceiver |
| 78Q2120-64T | 10/100BASE-TX Ethernet Transceiver |
| 78Q2120-CGT | 10/100BASE-TX Ethernet Transceiver |
| 78Q8392L | Low Power Ethernet Coaxial Transceiver |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 78Q2120-64CG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100BASE-TX Ethernet Transceiver |
| 78Q2120-64CGT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100BASE-TX Ethernet Transceiver |
| 78Q2120-64T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100BASE-TX Ethernet Transceiver |
| 78Q2120C | 制造商:TDK 制造商全稱:TDK Electronics 功能描述:10/100BASE - TX Transceiver |
| 78Q2120C09-64CGT | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:10/100BASE-TX Transceiver |
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