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參數(shù)資料
| 型號： | 78P2351-IGT/F |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 42/42頁 |
| 文件大小： | 0K |
| 描述： | LINE INTERFACE UNIT 100-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | E4，OC-3，STM1-E |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（16x16） |
| 包裝： | 托盤 |
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78P2351
Single Channel
OC-3/ STM1-E/ E4 LIU
Page: 9 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
SERIAL CONTROL INTERFACE
The serial port controlled register allows a generic
controller to interface with the 78P2351. It is used
for mode settings, diagnostics and test, retrieval of
status and performance information, and for on-chip
fuse trimming during production test. The SPSL pin
must be high in order to use the serial port.
The serial interface consists of four pins: Serial Port
Enable (SEN_CMI), Serial Clock (SCK_MON), Serial
Data In (SDI_PAR), and Serial Data Out (SDO_E4).
The SEN_CMI pin initiates the read and write
operations.
It can also be used to select a
particular device allowing SCK_MON, SDI_PAR
and SDO_E4 to be bussed together.
SCK_MON is the clock input that times the data
on SDI_PAR and SDO_E4. Data on SDI_PAR
is latched in on the rising-edge of SCK_MON,
and data on SDO_E4 is clocked out using the
falling edge of SCK_MON.
SDI_PAR is used to insert mode, address, and
register data into the chip. Address and Data
information are input least significant bit (LSB)
first. The mode and address bit assignment and
register table are shown in the following section.
SDO_E4 is a tri-state capable output. It is used
to output register data during a read operation.
SDO_E4 output is normally high impedance,
and is enabled only during the duration when
register data is being clocked out. Read data is
clocked out least significant bit (LSB) first.
If SDI_PAR coming out of the micro-controller chip is
also tri-state capable, SDI_PAR and SDO_E4 can
be connected together to simplify connections.
PROGRAMMABLE INTERRUPTS
In addition to the receiver LOS and LOL status pins,
the 78P2351 provides a programmable interrupt for
the transmitter. In HW control mode, the default
functions of the Tx interrupt is a transmit Loss of
Lock (TXLOL) or FIFO error (FERR).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 78P2351-IGTR | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Single Channel OC-3/ STM1-E/ E4 LIU |
| 78P2351-IGTR/F | 功能描述:接口 - 專用 Single Ch OC-3/STM-1e/E4 LIU RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| 78P2351R | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Serial 155M NRZ to CMI Converter |
| 78P2351R-DB | 功能描述:界面開發(fā)工具 78P2351R Demo Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| 78P2351R-IM | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Serial 155M NRZ to CMI Converter |
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