2006 Teridian Semiconductor Corporation Rev." />
參數(shù)資料
型號(hào): 78P2351-IGT/F
廠商: Maxim Integrated Products
文件頁數(shù): 3/42頁
文件大?。?/td> 0K
描述: LINE INTERFACE UNIT 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: E4,OC-3,STM1-E
電源電壓: 3.15 V ~ 3.45 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(16x16)
包裝: 托盤
78P2351
Single Channel
OC-3/ STM1-E/ E4 LIU
Page: 11 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
REGISTER DESCRIPTION (continued)
LEGEND
TYPE
DESCRIPTION
TYPE
DESCRIPTION
R/O
Read only
R/W
Read or Write
R/C
Read and Clear
GLOBAL REGISTERS
ADDRESS 0-0: MASTER CONTROL REGISTER
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
7
E4
R/W
0
Line Rate Selection:
Selects the line rate as well as the input clock frequency at the
CKREFP/N pins.
0: OC-3, STS-3, STM-1 (155.52MHz)
1: E4 (139.264MHz)
6
--
R/W
0
Unused
5
PAR
R/W
0
Serial/Parallel Interface Selection:
Selects the interface to the framer.
0: Serial LVPECL
1: 4-bit Parallel CMOS
4:3
CKSL
[1:0]
R/W
XX
Reference Clock Frequency Selection:
Selects the reference clock frequency input at CKREFP/N pins.
11: 155.52MHz / 139.264MHz (differential LVPECL)
10: 77.76MHz / NA (single-ended CMOS)
00: 19.44MHz / 17.408MHz (single-ended LVPECL)
Secondary values correspond to E4 frequencies. Default values depend
on the CKSL pin selection upon reset or power up.
2:1
--
R/W
X0
Reserved.
0
SRST
R/W
0
Register Soft-Reset:
When this bit is set, all registers are reset to their default values. This
register bit is self-clearing.
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