Data Sheet U14121EJ2V0DS00
64
μ
PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
(2) 16-bit instructions (instructions in parentheses are combinations realized by describing AX as rp)
MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH,
POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW
Table 12-2. Instruction List by 16-Bit Addressing
Second Operand
First Operand
#word
AX
rp
rp'
saddrp
saddrp'
sfrp
!addr16
!!addr24
mem
[saddrp]
[%saddrg]
[WHL+]
byte
n
None
Note 2
AX
(MOVW)
ADDW
Note 1
(MOVW)
(XCHW)
(ADD)
Note 1
(MOVW)
(XCHW)
(ADDW)
Note 1
(MOVW)
Note 3
(XCHW)
Note 3
(ADDW)
Notes 1, 3
MOVW
(XCHW)
(ADDW)
Note 1
(MOVW)
XCHW
MOVW
XCHW
(MOVW)
(XCHW)
rp
MOVW
ADDW
Note 1
(MOVW)
(XCHW)
(ADDW)
Note 1
MOVW
XCHW
ADDW
Note 1
MOVW
XCHW
ADDW
Note 1
MOVW
XCHW
ADDW
Note 1
MOVW
SHRW
SHLW
MULU
Note 4
INCW
DECW
saddrp
MOVW
ADDW
Note 1
(MOVW)
Note 3
(ADDW)
Note 1
MOVW
ADDW
Note 1
MOVW
XCHW
ADDW
Note 1
INCW
DECW
sfrp
MOVW
ADDW
Note 1
MOVW
(ADDW)
Note 1
MOVW
ADDW
Note 1
PUSH
POP
!addr16
!!addr24
MOVW
(MOVW)
MOVW
MOVTBLW
mem
[saddrp]
[%saddrg]
MOVW
PSW
PUSH
POP
SP
ADDWG
SUBWG
post
PUSH
POP
PUSHU
POPU
[TDE+]
(MOVW)
SACW
byte
MACW
MACSW
Notes 1.
The operands of SUBW and CMPW are the same as that of ADDW.
2.
Either the second operand is not used, or the second operand is not an operand address.
3.
The code length of some instructions having saddrp2 as saddrp in this combination is short.
4.
The operands of MULUW and DIVUX are the same as that of MULW.
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