參數(shù)資料
型號(hào): 74VHC125MX_NL
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Quad Buffer with 3-STATE Outputs
中文描述: AHC/VHC SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14
封裝: 0.150 INCH, LEAD FREE, MS-012, SOIC-14
文件頁數(shù): 1/8頁
文件大小: 61K
代理商: 74VHC125MX_NL
74VHC125
QUAD BUS BUFFERS (3-STATE)
PRELIMINARY DATA
June 1999
PIN CONNECTION AND IEC LOGIC SYMBOLS
I
HIGHSPEED:t
PD
=3.8ns(TYP.)atV
CC
= 5V
I
LOWPOWERDISSIPATION:
I
CC
=4
μ
A(MAX.) at T
A
=25
o
C
I
HIGHNOISEIMMUNITY:
V
NIH
= V
NIL
=28%V
CC
(MIN.)
I
POWERDOWN PROTECTIONON INPUTS
I
SYMMETRICALOUTPUTIMPEDANCE:
|I
OH
| = I
OL
= 8 mA(MIN)
I
BALANCEDPROPAGATIONDELAYS:
t
PLH
t
PHL
I
OPERATINGVOLTAGERANGE:
V
CC
(OPR)= 2Vto 5.5V
I
PINANDFUNCTION COMPATIBLEWITH
74SERIES125
I
IMPROVEDLATCH-UP IMMUNITY
I
LOWNOISE:V
OLP
= 0.8V(Max.)
DESCRIPTION
The 74VHC125 is an advanced high-speed
CMOS QUAD BUS BUFFERS fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
This device requires the 3-STATE control input G
to be set high to place the output into the high
impedancestate.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface5V to 3V.
All
inputs
and
outputs are
protection circuits against static discharge, giving
them 2kV ESD immunity and transient excess
voltage.
equipped with
ORDER CODES :
74VHC125M
74VHC125T
M
(Micro Package)
T
(TSSOPPackage)
1/8
相關(guān)PDF資料
PDF描述
74VHC125 Quad Bus Buffers (3-State)(四總線緩沖器)
74VHC126M Quadruple 2-Input Exclusive-OR Gates 14-SOIC -40 to 85
74VHC126T Quadruple 2-Input Exclusive-OR Gates 14-SOIC -40 to 85
74VHC126 Quad Bus Buffers (3-State)(四總線緩沖器)
74VHC132T Quadruple 2-Input Exclusive-OR Gates 14-TSSOP -40 to 85
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