參數(shù)資料
型號(hào): 74VHC125
廠商: 意法半導(dǎo)體
英文描述: Quad Bus Buffers (3-State)(四總線緩沖器)
中文描述: 四總線緩沖器(三態(tài))(四總線緩沖器)
文件頁(yè)數(shù): 1/8頁(yè)
文件大小: 69K
代理商: 74VHC125
74VHC125
QUAD BUS BUFFERS (3-STATE)
PRELIMINARY DATA
September 1998
PINCONNECTION AND IEC LOGICSYMBOLS
I
HIGH SPEED:t
PD
= 3.8 ns(TYP.) at V
CC
=5V
I
LOWPOWER DISSIPATION:
I
CC
= 4
μ
A (MAX.) at T
A
=25
o
C
I
HIGH NOISEIMMUNITY:
V
NIH
=V
NIL
=28%V
CC
(MIN.)
I
POWERDOWN PROTECTION ON INPUTS
I
SYMMETRICALOUTPUT IMPEDANCE:
|I
OH
| = I
OL
=8 mA (MIN)
I
BALANCED PROPAGATIONDELAYS:
t
PLH
t
PHL
I
OPERATINGVOLTAGERANGE:
V
CC
(OPR)= 2Vto5.5V
I
PIN AND FUNCTION COMPATIBLEWITH
74SERIES125
I
IMPROVEDLATCH-UP IMMUNITY
I
LOWNOISE:V
OLP
= 0.8V(Max.)
DESCRIPTION
The 74VHC125 is an advanced high-speed
CMOS QUAD BUS BUFFERS fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology. It has similar high
speed
performance
of
equivalent
Bipolar
Schottky TTL combined with true CMOS low
powerdissipation.
This device requires the 3-STATE control input G
to be set high to place the output into the high
impedancestate.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
usedto interface 5V to 3V.
All
inputs and
outputs
protectioncircuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
are
equipped with
ORDER CODES :
74VHC125M
74VHC125T
M
(MicroPackage)
T
(TSSOP Package)
1/8
相關(guān)PDF資料
PDF描述
74VHC126M Quadruple 2-Input Exclusive-OR Gates 14-SOIC -40 to 85
74VHC126T Quadruple 2-Input Exclusive-OR Gates 14-SOIC -40 to 85
74VHC126 Quad Bus Buffers (3-State)(四總線緩沖器)
74VHC132T Quadruple 2-Input Exclusive-OR Gates 14-TSSOP -40 to 85
74VHC132M Quadruple 2-Input Exclusive-OR Gates 14-SOIC -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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